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參數(shù)資料
| 型號： | MC141627FT |
| 廠商： | MOTOROLA INC |
| 元件分類： | 信號分離 |
| 英文描述： | Military Digital Signal Processor 172-CFP |
| 中文描述： | Y/C SEPARATOR IC, PQFP48 |
| 封裝： | QFP-48 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 236K |
| 代理商： | MC141627FT |
MC141627
5
MOTOROLA
ADC – DAC GENERAL CHARACTERISTICS
(VCC = 5.0 V, TA = 25
°
C
±
3
°
C)
Characteristic
Symbol
Min
Typ
Max
Unit
Voltage Gain
—
– 4.4
—
dB
Output Bandwidth (at – 3 dB at PAL)
6.4
7.3
—
MHz
Differential Gain
DG
—
—
5
%
Differential Phase
DP
—
—
5
Deg
Bias Current (at Ibias = 10 k
)
Ibias
—
135
—
μ
A
CLAMP CIRCUIT CHARACTERISTICS
(VCC = 5.0 V, TA = 25
°
C
±
3
°
C)
Characteristic
Symbol
Min
Typ
Max
Unit
Clamp Mode Output Voltage*
Vclys
—
0.6
—
V
* Output of CLout when connecting Vin – CLout.
BK/VH CHARACTERISTICS
(VCC = 5.0 V, TA = 25
°
C
±
3
°
C)
Characteristic
Symbol
Min
Typ
Max
Unit
Bypass Switching Time, at Normal Mode
—
9
—
Clock
VH Switching Time, at Normal Mode
—
4
—
Clock
Comb/BPF Switching Time, at Normal Mode
—
16
—
Clock
VERTICAL ENHANCER LEVEL CHARACTERISTICS
(VCC = 5.0 V, TA = 25
°
C
±
3
°
C)
Characteristic
Symbol
Min
Typ
Max
Unit
Noise Slice Level, at Normal Mode
0
6
15
Bits
White Enhance Level, at Normal Mode
0
10
15
Bits
Black Enhance Level, at Normal Mode
0
11
15
Bits
GENERAL SIGNAL DELAY
(VCC = 5.0 V, TA = 25
°
C
±
3
°
C)
Characteristic
Symbol
Min
Typ
Max
Unit
PAL B/G/H/I Mode (2299.5 Clock)
—
129.66
—
μ
s
NTSC Mode (939.5 Clock)
—
65.62
—
μ
s
PAL N Mode (1867.5 Clock)
—
130.34
—
μ
s
PAL M Mode (1851.5 Clock)
—
129.45
—
μ
s
Figure 1. Digital Signal Input Timing Diagram (During Digital Input Comb Filter Mode)
INPUT DATA
(D0 – D7)
CLOCK
tds
tdh
tr
tf
Clamp Circuit Characteristics
(VCC = 5.0 V, TA = 25
°
C
±
3
°
C)
Clamp Mode Output Voltage, Vcly (Non–input when connecting Vin – CLout)
Vcly = (VTP – VBT) (N + 1) / 256 + VBT
±
50 mV
where N = Clamp Code Input (N < 255)
If the calculated value of the output voltage, Vcly > Vclys, then Vcly = Vclys
Clamp Value N is fixed, N = 4.
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