Semiconductor Components Industries, LLC, 2013
May, 2013 Rev. 8
1
Publication Order Number:
MC14175B/D
MC14175B
Quad Type D Flip-Flop
The MC14175B quad type D flipflop is constructed with MOS
Pchannel and Nchannel enhancement mode devices in a single
monolithic structure. Each of the four flipflops is positiveedge
triggered by a common clock input (C). An activelow reset input (R)
asynchronously resets all flipflops. Each flipflop has independent
Data (D) inputs and complementary outputs (Q and Q). These devices
may be used as shift register elements or as type T flipflops for
counter and toggle applications.
Features
Complementary Outputs
Static Operation
All Inputs and Outputs Buffered
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Output Compatible with Two LowPower TTL Loads or One
LowPower Schottky TTL Load
Functional Equivalent to TTL 74175
These Devices are PbFree and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
VDD
0.5 to +18.0
V
Input or Output Voltage Range
(DC or Transient)
Vin, Vout
0.5 to VDD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
Iin, Iout
±10
mA
Power Dissipation per Package (Note
1)PD
500
mW
Ambient Temperature Range
TA
55 to +125
°C
Storage Temperature Range
65 to +150
°C
Lead Temperature (8Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
Device
Package
Shipping
ORDERING INFORMATION
http://onsemi.com
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
MC14175BFELG SOEIAJ16
(PbFree)
2000/Tape & Reel
MC14175BDR2G
SOIC16
(PbFree)
2500/Tape & Reel
MC14175BDG
SOIC16
(PbFree)
48 Units/Rail
MC14175BCPG
PDIP16
(PbFree)
500 Units/Rail
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= PbFree Package
MARKING
DIAGRAMS
PDIP16
P SUFFIX
CASE 648
SOIC16
D SUFFIX
CASE 751B
1
16
14175BG
AWLYWW
SOEIAJ16
F SUFFIX
CASE 966
1
16
MC14175B
ALYWG
16
1
MC14175BCP
AWLYYWWG
1
NLV14175BDR2G SOIC16
(PbFree)
2500/Tape & Reel