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參數(shù)資料
| 型號： | MC14458 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Encoder and Decoder Pairs |
| 中文描述： | 編碼器和解碼器雙 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 233K |
| 代理商： | MC14458 |
MC145026
MC145027
MC145028
SC41343
SC41344
14
MOTOROLA
MC145027 AND MC145028 TIMING
To verify the MC145027 or MC145028 timing, check the
waveforms on C1 (Pin 7) and R2/C2 (Pin 10) as compared to
the incoming data waveform on Din (Pin 9).
The R–C decay seen on C1 discharges down to 1/3 VDD
before being reset to VDD. This point of reset (labelled “DOS”
in Figure 15) is the point in time where the decision is made
whether the data seen on Din is a 1 or 0. DOS should not be
too close to the Din data edges or intermittent operation may
occur.
The other timing to be checked on the MC145027 and
MC145028 is on R2/C2 (see Figure 16). The R–C decay is
continually reset to VDD as data is being transmitted. Only
between words and after the end–of–transmission (EOT)
does R2/C2 decay significantly from VDD. R2/C2 can be used
to identify the internal end–of–word (EOW) timing edge which
is generated when R2/C2 decays to 2/3 VDD. The internal
EOT timing edge occurs when R2/C2 decays to 1/3 VDD.
When the waveform is being observed, the R–C decay
should go down between the 2/3 and 1/3 VDD levels, but not
too close to either level before data transmission on Din re-
sumes.
Verification of the timing described above should ensure a
good match between the MC145026 transmitter and the
MC145027 and MC145028 receivers.
VDD
0 V
Din
VDD
2/3
1/3
0 V
C1
DOS
DOS
Figure 15. R–C Decay on Pin 7 (C1)
VDD
2/3
1/3
0 V
R2/C2
EOT
Figure 16. R–C Decay on Pin 10 (R2/C2)
EOW
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