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參數(shù)資料
| 型號(hào)： | MC145053P |
| 廠商： | MOTOROLA INC |
| 元件分類： | ADC |
| 英文描述： | -48V Hot Swap Controller 8-MSOP -40 to 85 |
| 中文描述： | 5-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 166K |
| 代理商： | MC145053P |
MC145053
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
7
on the first four rising edges of SCLK, and the previous 10-bit
conversion result is shifted out on the first nine falling edges
of SCLK. After the fourth rising edge of SCLK, the new mux
address is available; therefore, on the next edge of SCLK
(the fourth falling edge), the analog input voltage on the
selected mux input begins charging the RC DAC and con-
tinues to do so until the tenth falling edge of SCLK. After this
tenth SCLK edge, the analog input voltage is disabled from
the RC DAC and the RC DAC begins the “hold” portion of the
A/D conversion sequence. Also upon this tenth SCLK edge,
control of the internal circuitry is transferred to the internal
clock oscillator which drives the successive approximation
logic to complete the conversion. If 16 SCLK cycles are used
during each transfer, then there is a constraint on the mini-
mum SCLK frequency. Specifically, there must be at least
one rising edge on SCLK before the A/D conversion is com-
plete. If the SCLK frequency is too low and a rising edge
does not occur during the conversion, the chip is thrown out
of sync with the processor and CS needs to be toggled in or-
der to restore proper operation. If 10 SCLKs are used per
transfer, then there is no lower frequency limit on SCLK. Also
note that if the ADC is operated such that CS is inactive high
between transfers, then the number of SCLK cycles per
transfer can be anything between 10 and 16 cycles, but the
“rising edge” constraint is still in effect if more than 10 SCLKs
are used. (If CS stays active low for multiple transfers, the
number of SCLK cycles must be either 10 or 16.)
EOC
End-of-Conversion Output (Pin 1)
EOC goes low on the tenth falling edge of SCLK. A low-to-
high transition on EOC occurs when the A/D conversion is
complete and the data is ready for transfer.
ANALOG INPUTS AND TEST MODES
AN0 through AN4
Analog Multiplexer Inputs (Pins 2 – 6)
The input AN0 is addressed by loading $0 into the mux
address register. AN1 is addressed by $1, AN2 by $2, AN3
by $3, and AN4 by $4. Table 2 shows the input format for a
16-bit stream. The mux features a break-before-make
switching structure to minimize noise injection into the ana-
log inputs. The source resistance driving these inputs must
be
1 k
.
During normal operation, leakage currents through the
analog mux from unselected channels to a selected channel
and leakage currents through the ESD protection diodes on
the selected channel occur. These leakage currents cause
an offset voltage to appear across any series source resis-
tance on the selected channel. Therefore, any source resis-
tance greater than 1 k
(Motorola test condition) may induce
errors in excess of guaranteed specifications.
There are three tests available that verify the functionality
of all the control logic as well as the successive approxima-
tion comparator. These tests are performed by addressing
$B, $C, or $D and they convert a voltage of (Vref + VAG)/2,
VAG, or Vref, respectively. The voltages are obtained internal-
ly by sampling Vref or VAG onto the appropriate elements of
the RC DAC during the sample phase. Addressing $B, $C, or
$D produces an output of $200 (half scale), $000, or $3FF
(full scale), respectively, if the converter is functioning prop-
erly. However, deviation from these values occurs in the
presence of sufficient system noise (external to the chip) on
VDD, VSS, Vref, or VAG.
POWER AND REFERENCE PINS
VSS and VDD
Device Supply Pins (Pins 7 and 14)
VSS is normally connected to digital ground; VDD is con-
nected to a positive digital supply voltage. Low frequency
(VDD – VSS) variations over the range of 4.5 to 5.5 volts do
not affect the A/D accuracy. (See the Operations Ranges
Table for restrictions on Vref and VAG relative to VDD and
VSS.) Excessive inductance in the VDD or VSS lines, as on
automatic test equipment, may cause A/D offsets >
±
1 LSB.
Use of a 0.1
μ
F bypass capacitor across these pins is recom-
mended.
VAG and Vref
Analog Reference Voltage Pins (Pins 8 and 9)
Analog reference voltage pins which determine the lower
and upper boundary of the A/D conversion. Analog input volt-
ages
≥
Vref produce a full scale output and input voltages
≤
VAG produce an output of zero. CAUTION: The analog
input voltage must be
≥
VSS and
≤
VDD. The A/D conversion
result is ratiometric to Vref – VAG. Vref and VAG must be as
noise-free as possible to avoid degradation of the A/D
conversion. Ideally, Vref and VAG should be single-point con-
nected to the voltage supply driving the system’s transduc-
ers. Use of a 0.22
μ
F bypass capacitor across these pins is
strongly urged.
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