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參數(shù)資料
| 型號： | MC145073DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | ADC |
| 英文描述： | Dual 16-Bit Stereo Audio Sigma-Delta ADC |
| 中文描述： | 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOG-24 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 224K |
| 代理商： | MC145073DW |
MC145073
12
MOTOROLA
Operation with the MC145073 as a Master (ISLAV = 0)
When ISLAV = 0, the SYNC and SCLK signals are defined
as outputs, and the MC145073 is configured as master
device. In this mode there are eight possible serial formats
as illustrated in Figure 10. The phase of the SYNC output
can precede the serial output data by one SCLK cycle (com-
patible with DSP56000/56001, TMS320, and I2S interface
format), or the SYNC signal can be coincident with the serial
output data (similar to the CS5326 serial interface format).
As shown in Figure 10, with each of these two SYNC formats
there are four possible formats for the serial output data.
Serial output data is shifted out MSB first, with left channel
data preceding the right channel data. All of the serial inter-
face outputs, SYNC, SCLK, and SDO are initiated by a CLKI
rising edge. There are 128 CLKI cycles, and 64 SCLK cycles
per output data cycle. Multiplexing of two MC145073s is not
feasible in the master mode since the exact phase of the out-
put cannot be controlled.
NOTE
The serial data in one output cycle represents
data that was simultaneously sampled on the two
analog input channels.
It is possible to initiate the device in the slave mode de-
scribed in the
Operation with the MC145073 as a Slave
(ISLAV = 1)
section, and then switch to master mode. Once
set, the phase of SYNC should not change.
Operation with the MC145073 as a Slave (ISLAV = 1)
When ISLAV = 1 the SYNC and SCLK signals are defined
as inputs, and the MC145073 is configured as a slave de-
vice. However, the slave mode of the MC145073 is not a true
slave mode since the SYNC and SCLK inputs are reclocked
by the internal sample clock, CLKI. These internal reclocked
versions of SYNC and SCLK are shown in Figure 11, in addi-
tion to the external SYNC and SCLK signals.
Similar to the master mode of the previous section, there
are two formats for the SYNC signal, and four SDO formats,
yielding eight possible slave modes.
Multiplexing of two MC145073s in the slave mode is per-
formed by forcing IDOE low on both MC145073s, and forcing
IJUST high on one MC145073 and low on the other.
NOTE
When multiplexing two MC145073s, the mas-
ter clock divide by 1 mode should be used
(CSEL1,0 = 0,1) so that the exact phase of CLKI
is determined.
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