參數(shù)資料
型號: MC14515BDW
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: 4-Bit Transparent Latch/4-to-16 Line Decoder
中文描述: 4000/14000/40000 SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO24
封裝: SOIC-24
文件頁數(shù): 1/8頁
文件大小: 254K
代理商: MC14515BDW
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
385
MC14514B MC14515B
The MC14514B and MC14515B are two output options of a 4 to 16 line
decoder with latched inputs. The MC14514B (output active high option)
presents a logical “1” at the selected output, whereas the MC14515B (output
active low option) presents a logical “0” at the selected output. The latches
are R–S type flip–flops which hold the last input data presented prior to the
strobe transition from “1” to “0”. These high and low options of a 4–bit latch/4
to 16 line decoder are constructed with N–channel and P–channel
enhancement mode devices in a single monolithic structure. The latches are
R–S type flip–flops and data is admitted upon a signal incident at the strobe
input, decoded, and presented at the output.
These complementary circuits find primary use in decoding applications
where low power dissipation and/or high noise immunity is desired.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS*
Symbol
Parameter
VDD
DC Supply Voltage
Vin, Vout
Input or Output Voltage (DC or Transient)
Iin, Iout
Input or Output Current (DC or Transient),
per Pin
Value
Unit
– 0.5 to + 18.0
V
0.5 to VDD + 0.5
±
10
V
mA
PD
Tstg
TL
Power Dissipation, per Package
500
mW
Storage Temperature
– 65 to + 150
C
Lead Temperature (8–Second Soldering)
260
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
BLOCK DIAGRAM
VDD = PIN 24
VSS = PIN 12
4 TO 16
DECODER
TRANSPARENT
LATCH
STROBE
INHIBIT
2
3
1
21
22
23
DATA 1
DATA 2
DATA 3
DATA 4
A
B
C
D
20
19
14
17
18
4
5
6
7
8
10
9
11
16
15
13
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Data Inputs
Selected Output
MC14514 = Logic “1”
MC14515 = Logic “0”
Inhibit
D
C
B
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
S0
S1
S2
S3
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
X
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
X
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
All Outputs = 0, MC14514
All Outputs = 1, MC14515
DECODE TRUTH TABLE
(Strobe = 1)*
X = Don’t Care
*Strobe = 0, Data is latched
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 623
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
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