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參數(shù)資料
| 型號： | MC145162P1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | One Inverting, One Non-inverting AND Dual High-Speed MOSFET Drivers 8-SOIC |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 85 MHz, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 223K |
| 代理商： | MC145162P1 |
MC145162
MC145162–1
MOTOROLA
13
POWER SAVING OPERATION
This PLL has a programmable power–saving scheme. The
transmit and receive counters and the reference frequency
counter can be powered down individually by setting the
TxPD enable, RxPD enable, and Ref PD enable bits of the
control register. The functions of the power down control bits
are explained in Table 2 and the programming format is in
Figure 8.
The output pins TxPS/fTx and RxPS/fRx output the status of
the internal power saving setting. If the bit TxPD enable is set
“high” (transmit counter is set to power–down mode), then the
TxPS/fTx pin will also output a “high” state. This TxPS/fTx out-
put can control an external power switch to switch off the
transmitter, as shown in Figure 17. This scheme can be
applied to the RxPS/fRx output to control the receiver power
saving operation as required.
Figure 17. TxPS/fTx and RxPS/fRx Outputs to Control Power Switches
of the Transmitter and the Receiver
Q
Q
POWER SWITCH FOR TRANSMITTER
VDD
UNIVERSAL DUAL PLL
RxPS/fRx
TxPS/fTx
POWER SUPPLY
Tx
POWER
AMP
Tx DIVIDER CHAIN COUNTER, PHASE DETECTOR
Tx POWER–DOWN
ENABLE FLAG
Rx DIVIDER CHAIN COUNTER, PHASE DETECTOR
Rx POWER–DOWN
ENABLE FLAG
VDD
TO CONTROL THE RECEIVER
POWER SWITCH
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC145166DW | 制造商:Motorola Inc 功能描述:PLL FREQUENCY SYNTHESIZER, 60 MHz, PDSO16 |
| MC145167DW | 制造商:Motorola Inc 功能描述:PLL FREQUENCY SYNTHESIZER, 60 MHz, PDSO16 |
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