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參數(shù)資料
| 型號： | MC145166 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLLs for 46/49 MHz Cordless Telephones |
| 中文描述： | 為46/49兆赫無繩電話雙PLL |
| 文件頁數(shù)： | 3/11頁 |
| 文件大小： | 135K |
| 代理商： | MC145166 |
MC145166
MC145167
MOTOROLA
3
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
Rating
Value
Unit
VDD
Vin
Iin, Iout
IDD, ISS
Tstg
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
DC Supply Voltage
– 0.5 to + 6.0
V
Input Voltage, All Inputs
– 0.5 to VDD + 0.5
10
V
DC Current Drain Per Pin
mA
DC Current Drain VDD or VSS Pins
Storage Temperature Range
30
mA
– 65 to + 150
°
C
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS, TA = 25
°
C)
Symbol
b l
Characteristic
i i
VDD
Guaranteed Limit
U i
Unit
Min
Max
VDD
VOL
Power Supply Voltage Range
—
2.5
5.5
V
Output Voltage
(Iout = 0)
0 Level
2.5
5.5
—
—
0.05
0.05
V
VOH
(Vin = VDD or 0)
1 Level
2.5
5.5
2.45
5.45
—
—
VIL
Input Voltage
(Vout = 0.5 V or VDD – 0.5 V)
0 Level
2.5
5.5
—
—
0.75
1.65
V
VIH
1 Level
2.5
5.5
1.75
3.85
—
—
IOH
Output Current
(Vout = 2.2 V)
(Vout = 5.0 V)
Source
2.5
5.5
– 0.18
– 0.55
—
—
mA
IOL
(Vout = 0.3 V)
(Vout = 0.5 V)
Sink
2.5
5.5
0.18
0.55
—
—
IIL
Input Current
(Vin = 0)
OSCin, fin1, fin2
2.5
5.5
—
—
– 30
– 66
μ
A
DATA, SB, Mode
2.5
5.5
—
—
– 0.05
– 0.11
IIH
(Vin = VDD – 0.5)
OSCin, fin1, fin2
2.5
5.5
—
—
30
66
μ
A
DATA, SB, Mode
2.5
5.5
—
—
50
121
Cin
Cout
IDD
Input Capacitance
—
—
14.0
pF
Output Capacitance
—
—
8.0
pF
Standby Current, SB = VSS or Open
2.5
5.5
—
—
1.4
3.6
mA
Idd
Operating Current
(200 mV p–p input at fin1 and fin2, SB = VDD)
2.5
5.5
—
—
2.8
6.2
mA
IOZ
Three–State Leakage Current
(Vout = 0 or 5.5 V)
5.5
—
±
1.0
μ
A
This device contains protection circuitry to
guard against damage due to high static volt-
ages or electric fields. However, precautions
must be taken to avoid applications of any
voltage higher than maximum rated voltages
to this high–impedance circuit. For proper oper-
ation, Vin and Vout should be constrained to
the range VSS
≤
(Vin or Vout)
≤
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
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