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參數(shù)資料
| 型號： | MC145170 |
| 廠商： | Motorola, Inc. |
| 英文描述： | PLL Frequency Synthesizer(PLL頻率發(fā)生器) |
| 中文描述： | 鎖相環(huán)頻率合成器（PLL頻率發(fā)生器） |
| 文件頁數(shù)： | 10/14頁 |
| 文件大小： | 173K |
| 代理商： | MC145170 |
10
MOTOROLA RF/IF APPLICATIONS INFORMATION
If the actual circuit is measured, the result varies
considerably from what is shown in Figure 19. The reason for
the difference is the same whenever any simulation fails to
track the actual circuit. It is an incomplete model. Unless the
model describes all parameters well enough to produce the
desired results, differences between the actual circuit and the
modeled circuit occur.
This example however is quite easy to correct. Normally,
parasitic components are not drawn on schematics. The
engineer is supposed to recognize that they exist and modify
his design and procedures accordingly. In this case, the
problem is the inductive component of the PCB trace
connecting the phase detector output, the loop filter
components and the VCO together and stray capacitance
from pads and jumpers. In an actual implementation of this
circuit (the MC145170EVK PCB), several jumpers are used
to select a variety of loop configurations. The contributions of
these jumpers and the PCB traces affect the phase detector
output. If the circuit is modifies (Figure 20), to include the
stray components (along with scope probe loading) and the
simulation rerun, the result tracks the actual circuit quite
closely (Figure 21).
Figure 20.
HB3
PWR
GND
PDout
Ref
In
HB1
GND
PWR
R2
10 k
R3
10 k
R1
10 k
820 p
R4
0
0
C3
C2
0
10 nF
GND
PWR
V1
5 V
+
–
0
50
R5
Ctrl
0
+
–
+
+
+
IC = 2.9921 V
390 pF
0
C1
V2
Out
VCOout
IC = 2.9921 V
IC = 2.9921 V
13 p
0
V
L2
R11
C7
15 p
C6
0
12 k
20 nH
1 meg
400
401
402
405
TIME ( s)
Figure 21.
V
3.2
3.0
2.8
2.6
2.4
2.2
403
404
Computing Resources
PSpice and other Spice simulators incorporating full
Berkley Spice compatibility require significant computing
power. When running PSpice on the PC, a Pentium
processor with RAM capability equal to or greater than that
recommended by MicroSim should be used. In addition,
large data files are generated when simulating high
resolution, long period transient analysis. Sufficient disk
space should be provided if spectrum analysis of the VCO is
to be performed. A gigabyte–sized drive is not too large for
this type of analysis.
Conclusion
Although PSpice is not blinding fast for some analysis
types and large data files can fill a drive if not properly
managed, simulating PLL circuits can provide the circuit
designer fast design and verification of synthesizer circuits.
While there is no substitute for building and testing the actual
circuit, many what–if conditions and basic design questions
can be answered by simulating first.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145170D1 | 制造商: 功能描述: 制造商:Motorola Inc 功能描述: 制造商:undefined 功能描述: |
| MC145170D2 | 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC145170D2R2 | 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC145170DT2 | 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MC145170DT2R2 | 功能描述:IC SERIAL PLL FREQ SYNTH 16TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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