Semiconductor Components Industries, LLC, 2013
May, 2013 Rev. 7
1
Publication Order Number:
MC14526B/D
MC14526B
Presettable 4-Bit Down
Counters
The MC14526B binary counter is constructed with MOS Pchannel
and Nchannel enhancement mode devices in a monolithic structure.
This device is presettable, cascadable, synchronous down counter
with a decoded “0” state output for dividebyN applications. In
single stage applications the “0” output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade dividebyN
operation with no additional gates required. The Inhibit input allows
disabling of the pulse counting function. Inhibit may also be used as a
negative edge clock.
This complementary MOS counter can be used in frequency
synthesizers, phaselocked loops, and other frequency division
applications requiring low power dissipation and/or high noise
immunity.
Features
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic EdgeClocked Design: Incremented on Positive Transition of
Clock or Negative Transition of Inhibit
Asynchronous Preset Enable
Capable of Driving Two LowPower TTL Loads or One LowPower
Schottky TTL Load Over the Rated Temperature Range
These Devices are PbFree and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
DC Supply Voltage Range
VDD
0.5 to +18.0
V
Input or Output Voltage Range
(DC or Transient)
Vin,
Vout
0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
Iin, Iout
±10
mA
Power Dissipation per Package (Note
1)
PD
500
mW
Operating Temperature Range
TA
55 to +125
°C
Storage Temperature Range
Tstg
65 to +150
°C
Lead Temperature
(8Second Soldering)
TL
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page
8 of this data sheet.
ORDERING INFORMATION
SOIC16 WB
DW SUFFIX
CASE 751G
MARKING
DIAGRAMS
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= PbFree Package
1
14526B
AWLYWWG
PDIP16
P SUFFIX
CASE 648
1
MC14526BCP
AWLYYWWG