參數(shù)資料
型號: MC14529BCP
廠商: MOTOROLA INC
元件分類: 運(yùn)動控制電子
英文描述: Non-inverting Fast Synchronous Buck MOSFET Drivers with TTL Inputs and Enable 14-HTSSOP -40 to 125
中文描述: DUAL 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 2/8頁
文件大?。?/td> 250K
代理商: MC14529BCP
MOTOROLA CMOS LOGIC DATA
MC14529B
2
Characteristic
Symbol
VDD
Test Conditions
Unit
Min
Max
Min
Typ #
Max
Min
Max
SUPPLY REQUIREMENTS
(Voltages Referenced to VEE)
Power Supply Voltage
Range
VDD
VDD – 3.0
VSS
VEE
3.0
18
3.0
18
3.0
18
V
Quiescent Current Per
Package
IDD
5.0
10
15
Control Inputs: Vin =
VSS or VDD,
Switch I/O: VSS
VI/O
VDD, and
Vswitch
500 mV**
1.0
1.0
2.0
0.005
0.010
0.015
1.0
1.0
2.0
60
60
120
μ
A
Total Supply Current
(Dynamic Plus
Quiescent, Per Package
ID(AV)
5.0
10
15
TA = 25 C only (The
channel component,
(Vin – Vout)/Ron, is
not included.)
(0.07
μ
A/kHz) f + IDD
(0.20
μ
A/kHz) f + IDD
(0.36
μ
A/kHz) f + IDD
Typical
μ
A
CONTROL INPUTS — INHIBIT, A, B
(Voltages Referenced to VSS)
Low–Level Input Voltage
VIL
5.0
10
15
Ron = per spec,
Ioff = per spec
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
V
High–Level Input Voltage
VIH
5.0
10
15
Ron = per spec,
Ioff = per spec
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
V
Input Leakage Current
Iin
Cin
15
Vin = 0 or VDD
±
0.1
±
0.00001
±
0.1
±
1.0
μ
A
Input Capacitance
5.0
7.5
pF
SWITCHES IN/OUT AND COMMONS OUT/IN — W, Z
(Voltages Referenced to VEE)
Recommended Peak–to–
Peak Voltage Into or
Out of the Switch
VI/O
Channel On or Off
0
VDD
0
VDD
0
VDD
Vp–p
Recommended Static or
Dynamic Voltage
Across the Switch**
(Figure 5)
Vswitch
Channel On
0
600
0
600
0
300
mV
Output Offset Voltage
VOO
Ron
Vin = 0 V, No Load
Vswitch
Vin = VIL or VIH
(Control), and Vin =
0 to VDD (Switch)
10
μ
V
ON Resistance
10
15
500 mV**,
400
240
120
80
480
270
560
350
ON Resistance Between
Any Two Channels
in the Same Package
Ron
10
15
15
10
Off–Channel Leakage
Current (Figure 10)
Ioff
15
Vin = VIL or VIH
(Control) Channel to
Channel or Any One
Channel
±
100
±
0.05
±
100
±
1000
nA
Capacitance, Switch I/O
CI/O
CO/I
CI/O
Inhibit = VDD
Inhibit = VDD
Pins Not Adjacent
Pins Adjacent
8.0
pF
Capacitance, Common O/I
20
pF
Capacitance, Feedthrough
(Channel Off)
0.15
0.47
pF
#Data labelled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
** For voltage drops across the switch (
Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum
Ratings are exceeded. (See first page of this data sheet.)
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