參數(shù)資料
型號: MC14530
廠商: Motorola, Inc.
英文描述: Dual 5-Input Majority Logic Gate
中文描述: 雙5輸入多數(shù)邏輯門
文件頁數(shù): 5/7頁
文件大?。?/td> 217K
代理商: MC14530
MOTOROLA CMOS LOGIC DATA
5
MC14530B
BASIC COMBINATIONAL FUNCTIONS
5–INPUT MAJORITY LOGIC GATE APPLICATIONS
DOUBLING THE WEIGHT OF INPUT VARIABLE A
BY TYING IT TO ANY TWO INPUTS
W
CORRELATION OF MULTIPLE SAMPLES
WITH A TEST BIT
The gate will have a “1” output if
the test bit To matches or corre-
lates with 3, 4 or 5 of the sample
bits S0–S4.
1. Majority Logic Gate Array
yielding the symmetric function
of 1 thru 7 variables true, out
of 7 input variables (X1... X7)
(e.g., if any two–input variables
are true (logical “1”), Z1 and
Z2 are true (logical “1”)
Each package labeled M5 is a single majority logic gate
using five inputs, A thru E, and one output Z.
A
B
C
D
E
W
0
M5
Z
A
B
C
D
E
W
1
M5
Z
A
B
C
W
0
1
0
M3
Z
A
B
C
W
1
1
0
M3
Z
A
B
C
W
1
1
1
OR3
Z
A
B
C
W
0
1
1
NOR3
Z
A
B
C
W
1
0
0
AND3
Z
A
B
C
W
0
0
0
NAND3
Z
5–INPUT MAJORITY GATES
3–INPUT MAJORITY GATES
3–INPUT OR GATE
3–INPUT AND GATE
3–INPUT NAND GATE
3–INPUT NOR GATE
A
B
C
D
E
M5
A
B
C
D
E
M5
A
B
C
D
E
M5
A
B
C
D
E
M5
A
B
C
D
E
M5
A
B
C
D
E
M5
A
B
C
D
E
M5
M5
M5
M5
M5
M5
M5
M5
M5
Z1
Z2
Z3
Z4
Z5
Z6
Z7
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
X1
X4
X6
X7
X5
X3
X2
A
A
B
C
D
Z
Z
Z
Z
W
A
B
C
D
E
To
S0
S1
S2
S3
S4
W
W
W
A
B
C
D
E
To
S0
S1
S2
S3
A
B
C
D
E
To
To
S0
S1
S2
CORRELATION OF 100%
CORRELATION OF 75%, 100%
CORRELATION OF 60%, 80%, 100%
(AB + AC + AD + BCD)
W
To
To
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