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參數(shù)資料
| 型號(hào)： | MC14538BDR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 諧振器 |
| 英文描述： | UltraLow-Supply Current/Supply-Voltage Supervisory Circuit 6-SOT-23 -40 to 85 |
| 中文描述： | 4000/14000/40000 SERIES, DUAL MONOSTABLE MULTIVIBRATOR, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 272K |
| 代理商： | MC14538BDR2 |
MOTOROLA CMOS LOGIC DATA
MC14538B
6
Figure 8. Typical Error of Pulse Width
Equation versus Temperature
Figure 9. Typical Error of Pulse Width
Equation versus Temperature
–2
–1
0
1
2
–60
–40
–20
0
20
40
60
80
100
120
140
TA, AMBIENT TEMPERATURE (
°
C)
T
W
D
°
C
RX = 100 k
CX = 0.1
μ
F
VDD = 15 V
VDD = 10 V
VDD = 5 V
–2.0
–1.0
0
1.0
2.0
3.0
–3.0
–60
–40
–20
0
20
40
60
80
100
120
140
TA, AMBIENT TEMPERATURE (
°
C)
RX = 100 k
CX = .002
μ
F
VDD = 15 V
VDD = 10 V
VDD = 5.0 V
T
W
D
°
C
THEORY OF OPERATION
2
Figure 10. Timing Operation
Positive edge re–trigger (pulse lengthening)
Positive edge trigger
1
2
3
4
5
1
3
4
5
RESET
A
B
CX/RX
Q
Vref 1
Vref 1
Vref 1
Vref 1
Vref 2
Vref 2
Vref 2
Vref 2
T
T
T
Negative edge trigger
Positive edge trigger
Positive edge re–trigger (pulse lengthening)
TRIGGER OPERATION
The block diagram of the MC14538B is shown in Figure 1,
with circuit operation following.
As shown in Figure 1 and 10, before an input trigger
occurs, the monostable is in the quiescent state with the Q
output low, and the timing capacitor CX completely charged
to VDD. When the trigger input A goes from VSS to VDD
(while inputs B and Reset are held to VDD) a valid trigger is
recognized, which turns on comparator C1 and N–channel
transistor N1
. At the same time the output latch is set. With
transistor N1 on, the capacitor CX rapidly discharges toward
VSS until Vref1 is reached. At this point the output of
comparator C1 changes state and transistor N1 turns off.
Comparator C1 then turns off while at the same time
comparator C2 turns on. With transistor N1 off, the capacitor
CX begins to charge through the timing resistor, RX, toward
VDD. When the voltage across CX equals Vref 2, comparator
C2 changes state, causing the output latch to reset (Q goes
low) while at the same time disabling comparator C2
. This
ends at the timing cycle with the monostable in the quiescent
state, waiting for the next trigger.
In the quiescent state, CX is fully charged to VDD causing
the current through resistor RX to be zero. Both comparators
are “off” with total device current due only to reverse junction
leakages. An added feature of the MC14538B is that the out-
put latch is set via the input trigger without regard to the
capacitor voltage. Thus, propagation delay from trigger to Q
is independent of the value of CX, RX, or the duty cycle of the
input waveform.
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| MC14538BDR2G | 功能描述:單穩(wěn)態(tài)多諧振蕩器 3-18V Dual Precision MonoStable RoHS:否 制造商:Texas Instruments 每芯片元件:1 邏輯系列:LVC 邏輯類型:Monostable Multivibrator 封裝 / 箱體:SSOP-8 傳播延遲時(shí)間:18.6 ns 高電平輸出電流:- 32 mA 低電平輸出電流:32 mA 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MC14538BDR2G-CUT TAPE | 制造商:ON 功能描述:MC14538B Series 3 to 18 Vdc Dual Precision Monostable - SOIC-16 |
| MC14538BDT | 制造商:ON Semiconductor 功能描述:Monostable Multivibrator Dual 16-Pin TSSOP Rail |
| MC14538BDTR2 | 功能描述:單穩(wěn)態(tài)多諧振蕩器 3-18V Dual Precision RoHS:否 制造商:Texas Instruments 每芯片元件:1 邏輯系列:LVC 邏輯類型:Monostable Multivibrator 封裝 / 箱體:SSOP-8 傳播延遲時(shí)間:18.6 ns 高電平輸出電流:- 32 mA 低電平輸出電流:32 mA 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MC14538BDTR2G | 功能描述:單穩(wěn)態(tài)多諧振蕩器 3-18V Dual Precision MonoStable RoHS:否 制造商:Texas Instruments 每芯片元件:1 邏輯系列:LVC 邏輯類型:Monostable Multivibrator 封裝 / 箱體:SSOP-8 傳播延遲時(shí)間:18.6 ns 高電平輸出電流:- 32 mA 低電平輸出電流:32 mA 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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