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參數(shù)資料
| 型號： | MC14543BFL1 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | 4000/14000/40000 SERIES, SEVEN SEGMENT DECODER/DRIVER, CONFIGURABLE OUTPUT, PDSO16 |
| 封裝： | EIAJ, PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 234K |
| 代理商： | MC14543BFL1 |
MC14543B
http://onsemi.com
4
SWITCHING CHARACTERISTICS (8.) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Min
Typ
Max
Unit
Output Rise Time
tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns
tTLH
5.0
10
15
—
100
50
40
200
100
80
ns
Output Fall Time
tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 12.5 ns
tTHL
5.0
10
15
—
100
50
40
200
100
80
ns
Turn–Off Delay Time
tPLH = (1.7 ns/pF) CL + 520 ns
tPLH = (0.66 ns/pF) CL + 217 ns
tPLH = (0.5 ns/pF) CL + 160 ns
tPLH
5.0
10
15
—
605
250
185
1210
500
370
ns
Turn–On Delay Time
tPHL = (1.7 ns/pF) CL + 420 ns
tPHL = (0.66 ns/pF) CL + 172 ns
tPHL = (0.5 ns/pF) CL + 130 ns
tPHL
5.0
10
15
—
505
205
155
1650
660
495
ns
Setup Time
tsu
5.0
10
15
350
450
500
—
ns
Hold Time
th
5.0
10
15
40
30
20
—
ns
Latch Disable Pulse Width (Strobing Data)
tWH
5.0
10
15
250
100
80
125
50
40
—
ns
8. The formulas given are for the typical characteristics only.
LOGIC DIAGRAM
VDD = PIN 16
VSS = PIN 8
B3
LD 1
D4
C2
A5
PHASE 6
14 g
15 f
13 e
12 d
11 c
10 b
9a
BI 7
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