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參數(shù)資料
| 型號： | MC14549BDWR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 2/9頁 |
| 文件大小： | 0K |
| 描述： | IC REGISTER 8BIT APPROX 16-SOIC |
| 標準包裝： | 1,000 |
| 系列： | 4000B |
| 邏輯類型： | 逐次近似寄存器 |
| 輸出類型： | 標準 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 8 |
| 功能： | 通用 |
| 電源電壓： | 3 V ~ 18 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
MC14549B, MC14559B
http://onsemi.com
2
SC SC(t1) MR MR(t1) Clock
Action
X
None
X
1
X
Reset
1
0
Start
Conversion
1
X
0
1
Start
Conversion
1
0
Continue
Conversion
0
X
0
X
Continue
Previous
Operation
TRUTH TABLES
MC14549B
X = Don’t Care t1 = State at Previous Clock
SC SC(t1) EOC Clock
Action
X
None
1
0
Start
Conversion
X
1
0
Continue
Conversion
0
Continue
Conversion
0
X
1
Retain
Conversion
Result
1
X
1
Start
Conversion
MC14559B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
VDD
Vdc
55_C
25_C
125_C
Unit
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Output Voltage
“0” Level
Vin = VDD or 0
VOL
5.0
10
15
0.05
0
0.05
0.05
Vdc
“1” Level
Vin = 0 or VDD
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage (Note 2)
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Vdc
Output Drive Current
(VOH = 2.5 Vdc)
Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH
5.0
10
15
– 1.2
– 0.25
– 0.62
– 1.8
– 1.0
– 0.2
0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
– 0.7
– 0.14
– 0.35
– 1.1
mAd
c
(VOL = 0.4 Vdc)
Sink
(VOL = 0.5 Vdc)
Q Outputs
(VOL = 1.5 Vdc)
IOL
5.0
10
15
1.28
3.2
8.4
1.02
2.6
6.8
1.76
4.5
17.6
0.72
1.8
4.8
mAd
c
(VOL = 0.4 Vdc)
Sink
(VOL = 0.5 Vdc)
Pin 5, 11 only
(VOL = 1.5 Vdc)
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAd
c
Input Current
Iin
15
±0.1
±0.00001
±0.1
±1.0
mAdc
Input Capacitance
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
(Clock = 0 V,
Other Inputs = VDD or 0 V, Iout = 0 mA)
IDD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
mAdc
Total Supply Current (Note 3, 4)
(Dynamic plus Quiescent,
Per Package) (CL = 50 pF on all
outputs, all buffers switching)
IT
5.0
10
15
IT = (0.8 mA/kHz) f + IDD
IT = (1.6 mA/kHz) f + IDD
IT = (2.4 mA/kHz) f + IDD
mAdc
2. Noise immunity specified for worstcase input combination.
Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V
= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V
3. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 3.5 x 103 (CL = 50) VDDf where: IT is in mA (per package),
CL in pF, VDD in V, and f in kHz is input frequency.
4. The formulas given are for the typical characteristics only at 25_C.
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