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MC145500
MC145501
MC145502
MC145503
MC145505
MOTOROLA
7
MODE CONTROL LOGIC
(VSS to VDD = 4.75 V to 12.6 V, TA = – 40 to + 85
°
C)
Characteristic
Min
Typ
Max
Unit
VLS Voltage for TTL Mode (TTL Logic Levels Referenced to VLS)
VLS Voltage for CMOS Mode (CMOS Logic Levels of VSS to VDD)
Mu/A Select Voltage
Mu–Law Mode
Sign Magnitude Mode
A–Law Mode
VSS
—
VDD – 4.0
VDD
V
VDD – 0.5
—
V
VDD – 0.5
VAG – 0.5
VSS
VDD – 0.5
VAG – 0.5
VSS
—
—
—
VDD
VAG + 0.5
VSS + 0.5
VDD
VAG + 0.5
VSS + 0.5
V
RSI Voltage for Reference Select Input (MC145501 and MC145502)
3.78 V Mode
2.5 V Mode
3.15 V Mode
—
—
—
V
Vref Voltage for Internal or External Reference (MC145502 Only)
Internal Reference Mode
External Reference Mode
VSS
VAG + 0.5
—
—
VSS + 0.5
VDD – 1.0
V
Analog Test Mode Frequency, MS = CCI (MC145500, MC145501, MC145502 Only)
See Pin Description; Test Modes
—
128
—
kHz
SWITCHING CHARACTERISTICS
(VSS to VDD = 9.5 V to 12.6 V, TA = – 40 to + 85
°
C, CL = 150 pF, CMOS or TTL Mode)
Characteristic
Symbol
Min
Typ
Max
Unit
Output Rise Time
Output Fall Time
TDD
tTLH
tTHL
—
—
30
30
80
80
ns
Input Rise Time
Input Fall Time
TDE, TDC, RCE, RDC, DC, MSI, CCI
tTLH
tTHL
—
—
—
—
4
4
μ
s
Pulse Width
TDE Low, TDC, RCE, RDC, DC, MSI, CCI
tw
fCL
fCL1
fCL2
fCL3
fCL4
fCL5
100
—
—
ns
DCLK Pulse Frequency (MC145502/05 Only)
TDC, RDC, DC
64
—
4096
kHz
CCI Clock Pulse Frequency (MSI = 8 kHz)
CCI is internally tied to TDC on the MC145500/01/03, therefore, the
transmit data clock must be one of these frequencies. This pin will accept
one of these discrete clock frequencies and will compensate to produce
internal sequencing.
—
—
—
—
—
128
1536
1544
2048
2560
—
—
—
—
—
kHz
Propagation Delay Time
TDE Rising to TDD Low Impedance
TTL
CMOS
TTL
CMOS
TTL
CMOS
TTL
CMOS
TDE Falling to TDD High Impedance
TDC Rising Edge to TDD Data, During TDE High
TDE Rising Edge to TDD Data, During TDC High
tP1
tP2
tP3
tP4
—
—
—
—
—
—
—
—
90
90
—
—
90
90
90
90
180
150
55
40
180
150
180
150
ns
TDC Falling Edge to TDE Rising Edge Setup Time
tsu1
tsu2
tsu8
tsu3
tsu4
tsu5
tsu6
tsu7
th
20
—
—
ns
TDE Rising Edge to TDC Falling Edge Setup Time
100
—
—
ns
TDE Falling Edge to TDC Rising Edge to Preserve the Next TDD Data
20
—
—
ns
RDC Falling Edge to RCE Rising Edge Setup Time
20
—
—
ns
RCE Rising Edge to RDC Falling Edge Setup Time
100
—
—
ns
RDD Valid to RDC Falling Edge Setup Time
60
—
—
ns
CCI Falling Edge to MSI Rising Edge Setup Time
20
—
—
ns
MSI Rising Edge to CCI Falling Edge Setup Time
100
—
—
ns
RDD Hold Time from RDC Falling Edge
100
—
—
ns
TDE, TDC, RCE, RDC, RDD, DC, MSI, CCI Input Capacitance
—
—
10
pF
TDE,TDC, RCE, RDC, RDD, DC, MSI, CCI Input Current
—
±
0.01
±
10
μ
A
TDD Capacitance During High Impedance (TDE Low)
—
12
15
pF
TDD Input Current During High Impedance (TDE Low)
—
±
0.1
±
10.0
μ
A