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參數(shù)資料
| 型號： | MC14562BCPG |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | 4000/14000/40000 SERIES, 128-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 178K |
| 代理商： | MC14562BCPG |
MC14562B
http://onsemi.com
4
Characteristic
Symbol
VDD
Min
Typ (7.)
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
5.0
10
15
—
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q
tPLH, tPHL = (1.7 ns/pF) CL + 515 ns
tPLH, tPHL = (0.66 ns/pF) CL + 217 ns
tPLH, tPHL = (0.5 ns/pF) CL + 145 ns
tPLH,
tPHL
5.0
10
15
—
600
250
170
1200
500
340
ns
Clock Pulse Width
(50% Duty Cycle)
tWH
5.0
10
15
600
220
150
300
110
75
—
ns
Clock Pulse Frequency
fcl
5.0
10
15
—
1.9
5.6
8.0
1.1
3.0
4.0
MHz
Data to Clock Setup Time
tsu(1)
5.0
10
15
– 20
– 10
0
– 170
– 64
– 60
—
ns
tsu(0)
5.0
10
15
– 20
– 10
0
– 91
– 58
– 48
—
ns
Data to Clock Hold Time
th(1)
5.0
10
15
350
165
155
263
109
100
—
ns
th(0)
5.0
10
15
350
200
140
267
140
93
—
ns
Clock Input Rise and Fall Times
tr, tf
5.0
10
15
—
15
5
4
μs
6. The formulas given are for the typical characteristics only at 25_C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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