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參數(shù)資料
| 型號： | MC14569BDWR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COUNTER DUAL 4BIT 4 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 4000B |
| 邏輯類型： | 除以 N |
| 元件數(shù)： | 2 |
| 每個元件的位元數(shù)： | 4 |
| 復(fù)位： | 異步 |
| 計數(shù)速率： | 13MHz |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 3 V ~ 18 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | MC14569BDWR2GOSCT |
Semiconductor Components Industries, LLC, 2013
May, 2013 Rev. 7
1
Publication Order Number:
MC14569B/D
MC14569B
Programmable Divide-By-N
Dual 4-Bit Binary/BCD
Down Counter
The MC14569B is a programmable dividebyN dual 4bit binary
or BCD down counter constructed with MOS PChannel and
NChannel enhancement mode devices (complementary MOS) in a
monolithic structure.
This device has been designed for use with the MC14568B phase
comparator/counter in frequency synthesizers, phaselocked loops,
and other frequency division applications requiring low power
dissipation and/or high noise immunity.
Features
Speedup Circuitry for Zero Detection
Each 4Bit Counter Can Divide Independently in BCD or Binary Mode
Can be Cascaded With MC14526B for Frequency Synthesizer
Applications
All Outputs are Buffered
Schmitt Triggered Clock Conditioning
These Devices are PbFree and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
0.5 to +18.0
V
Vin, Vout Input or Output Voltage Range
(DC or Transient)
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
55 to +125
°C
Tstg
Storage Temperature Range
65 to +150
°C
TL
Lead Temperature
(8Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING
DIAGRAMS
PDIP16
P SUFFIX
CASE 648
MC14569BCP
AWLYYWWG
SOIC16 WB
DW SUFFIX
CASE 751G
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
16
1
14569B
AWLYYWWG
16
1
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