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參數(shù)資料
| 型號： | MC145750VFU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | QPSK Encoder |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, VQFP-48 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 296K |
| 代理商： | MC145750VFU |
MC145750
6
MOTOROLA
ERST/PDN
External Reset/Power Down Input (Pin 48)
When a logic L is applied to this pin, it forces a complete
power down. When at start up, VDD goes high, it is recom-
mended that a logic L, then a logic H be applied to this pin to
start up and reset all digital portions.
ANALOG INTERFACE PINS
Qout
Filtered Quadrature–Phase Output (Pin 15)
This is the modulated quadrature–phase signal output and
the amplitude is typically 550 mV p–p at VDD = 3 V in PN test
mode. The output dc resistance is approximately 50
.
Iout
Filtered In–Phase Output (Pin 20)
This is the modulated in–phase signal output and ampli-
tude is typically 500 mV p–p at VDD = 3 V in PN test mode.
The output dc resistance is approximately 50
.
DAC AND PLL SETTING
DAb
Reference Bias Setting Pin to DACs (Pin 12)
A resistor connected to ground from this pin determines
the reference current value for internal DACs. This resistor’s
value is 200 k
typically.
DAref
Ripple Filter Capacitor (Pin 16)
A capacitor connected to ground from this pin acts as a rip-
ple filter for the internal DACs’ reference voltage. This capac-
itor’s value is 0.1
μ
F, typically.
DAref1 – DAref3
Reference Bias Setting to DACs (Pin 17 – 19)
These pins determine the reference voltage for internal
DACs in conjunction with DAb pin. At 3 V operation, DAref1
pin should be connected to VDD. DAref2 pin should be con-
nected to VDD at 3.3 V. DAref3 pin should be connected to
VDD at 5 V. The two other pins for the respective cases must
be left open.
PB1, PB2
PLL Bias (Pins 35, 38)
This pin determines the bias of the PLL. Its recommended
values are shown in Table 1 and it depends on operating volt-
age.
Cf
Loop Filter Capacitor (Pin 39)
Input from Cf pin is fed directly as the internal VCO control
signal.
PCO
Phase Comparator Output (Pin 40)
Connect an LPF as loop filter for the PLL. Refer to the ap-
plication figure for recommended values.
Table 1. Function Table
Pin
L
H
Remarks
3
MODE0
Normal Mode
PN Pattern
These settings are independent of power supply.
10
QPSK
Non–Shift
/4–Shift
9
DRATE
High Speed
Low Speed
To be determined setting high or low speed data rate.
17
DAref1
—
VDD = 5 V
VDD 3.3 V
VDD 3.0 V
These pins should be held high depending on power supply voltage and
others should be left open.
18
DAref2
—
19
DAref3
—
41
PLL
PLL Operation
Mode
Ext Clock Mode
In case of external clock mode, TX data rate must be set to a frequency
of 1/40 when DRATE = L, and must be set to a frequency of 1/320
when DRATE = H. Max data rate is limited by power supply.
48
ERST/PDN
Power Down
Normal Operation
Digital circuits reset condition will be released by rising edge of this
input.
Figure 2. DQPSK Baseband Signal Generation
SERIAL TO
PARALLEL
CONVERSION
DIFFERENTIAL
ENCODING
ROLL–OFF
FILTER
ROLL–OFF
FILTER
SERIAL DATA IN
Xk
Yk
Qk
Ik
TO DAC
TO DAC
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