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參數(shù)資料
| 型號(hào)： | MC14599BCL |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | 8-Bit Addressable Latches |
| 中文描述： | 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP18 |
| 封裝： | CERAMIC, DIP-18 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大小： | 287K |
| 代理商： | MC14599BCL |
MOTOROLA CMOS LOGIC DATA
MC14099B MC14599B
250
RESET
DATA
WRITE
DISABLE
A0
A1
A2
(M.S.B.)
7
6
5
4
3
2
CHIP
ENABLE
8
WRITE/READ 10
VSS
VDD
ADDRESS
DECODER
TO
OTHER
LATCHES
ZERO
SELECT
OTHER LATCHES
EACH LATCH
16 Q5
1
Q7
17 Q6
15 Q4
14 Q3
13 Q2
12 Q1
11 Q0
MC14599B
FUNCTION DIAGRAM
TRUTH TABLE
Chip
Enable
Write/Read
Write
Disable
Reset
Addressed
Latch
Other
Latches
Data
Pin
0
X
X
0
*
*
Z
1
1
0
0
Data
*
Input
1
1
1
0
*
*
Z
1
0
X
0
*
*
Qn
Z/0
X
X
X
1
0
0
X = Don’t care.
* = No change in state of latch.
Z = High impedance.
Qn = State of addressed latch.
CAUTION:
To avoid unintentional data changes in the latches, Write Disable must be active (high) during transitions on
the address inputs A0, A1, and A2.
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