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參數(shù)資料
| 型號(hào)： | MC14599BDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Battery-Backup Supervisor for Low Power Processor 10-MSOP -40 to 85 |
| 中文描述： | 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 287K |
| 代理商： | MC14599BDW |
MOTOROLA CMOS LOGIC DATA
249
MC14099B MC14599B
RESET
DATA
WRITE
DISABLE
A0
A1
A2
(M.S.B.)
7
6
5
4
3
2
ADDRESS
DECODER
TO
OTHER
LATCHES
ZERO
SELECT
OTHER LATCHES
EACH LATCH
14 Q5
1
Q7
15 Q6
13 Q4
12 Q3
11 Q2
10 Q1
9
Q0
MC14099B
FUNCTION DIAGRAM
TRUTH TABLE
Write
Disable
Reset
Addressed
Latch
Unaddressed
Latches
0
0
Data
Qn*
Reset
0
1
Data
1
0
Qn*
Reset
Qn*
Reset
1
1
* Qn is previous state of latch.
Reset to zero state.
SWITCHING WAVEFORMS
DATA OR
WRITE DISABLE
OUTPUT Q
RESET
OUTPUT Q
VDD
VSS
VDD
VSS
tPHL
50%
tTLH
tTHL
90%
50%
10%
50%
tPLH
tPHL
ADDRESS
WRITE
DISABLE
DATA
VDD
VSS
VDD
VSS
VDD
VSS
50%
50%
50%
tsu
tw(L)
trem
tsu
th
tw(H)
CAUTION:
To avoid unintentional data changes in the latches, Write
Disable must be active (high) during transitions on the
address inputs A0, A1, and A2.
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