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參數(shù)資料
| 型號： | MC14LC5004FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | Regulating Pulse-Width Modulators 16-SOIC 0 to 70 |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, PQFP52 |
| 封裝： | QFP-52 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 245K |
| 代理商： | MC14LC5004FU |
MOTOROLA
3–10
MC14LC5003 MC14LC5004
successive clock pulse, the addressed device will accept a
data bit.
If the ENB pin is permanently high, then the addressed
MC14LC5003’s internal counter latches the data to be dis-
played after 128 data bits have been received. Otherwise, the
control of this latch function may be overridden by holding the
ENB line low until the new data is required to be displayed,
then a high pulse should be sent on the ENB line. The high
pulse must be sent during DCLK high (clock idle).
To end communication with an MC14LC5003, a stop con-
dition should be set up on the bus (or another start condition
may be set up if another communication is desired). Note that
the communication channel to an addressed device may be
left open after the 128 data bits have been sent by not setting
up a stop or a start condition. In such a case, the 129th rising
DCLK edge, which normally would be used to set up the stop
or start condition, is ignored by the MC14LC5003 and data
continues to be received on the 130th rising DCLK. The latch
function continues to work as normal (i.e., data is be latched
either after each block of 128 data bits has been received or
under external control as required).
At any time during data transmission, the transfer may be
interrupted with a stop condition. Data transmission may be
resumed with a start condition and resending the address.
MC14LC5004 — IIC DEVICE (FIGURE 8)
Before communication with an MC14LC5004 can begin, a
start condition must be set up on the bus by the controller. To
establish a start condition, the controller must pull the data
line low while the clock line is high.
After the start condition has been established, an eight-bit
address should be sent by the controller followed by an extra
clock pulse while the data line is left high. In this option, only
the seven most significant bits of the address are used to
uniquely define devices on the bus, the least significant bit is
used as a read/write control: if the least significant bit is 0,
then the controller writes to the LCD driver; if it is 1, then the
controller reads from the LCD driver’s 128-bit shift register on
a first-in first-out basis. If the seven most significant address
bits sent correspond to the address of the LCD driver then the
addressed LCD driver responds by sending an “acknowledge”
bit back to the controller (i.e., the LCD driver pulls the data line
low during the extra clock pulse supplied by the controller). If
the least significant address bit was 0, then the controller
should continue to send data to the LCD driver in blocks of
eight bits followed by an extra ninth clock pulse to allow the
LCD driver to pull the data line D
in
low as an acknowledgment.
If the least significant address bit was 1, then the LCD driver
sends data back to the controller (the clock is supplied by the
controller). After each successive group of eight bits sent, the
LCD driver leaves the data line high for one pulse.
If the ENB pin is permanently high, then the addressed
MC14LC5004’s internal counter latches the data to be dis-
played after 128 data bits have been received. Otherwise the
control of this latch function may be overridden by holding the
ENB line low until the new data is required to be displayed,
then a high pulse should be sent on the ENB line. The high
pulse must be sent during DCLK high (clock idle).
To end communication with an MC14LC5004, a stop condi-
tion should be set up on the bus (or another start condition
may be set up if another communication is desired). Note that
the communication channel to an addressed device may be
left open after the 128 data bits have been sent by not setting
up a stop or a start condition. In such a case the rising DCLK
edge which comes after all 128 data bits have been sent and
after the last acknowledge-related clock pulse has been made
is ignored; data continues to be received on the following
DCLK high. The latch function continues to work as normal
(i.e., data is latched either after each block of 128 data bits
has been received or under external control as required).
At any time during data transmission, the transfer may be
interrupted with a stop condition. Data transmission may be
resumed with a start condition and resending the address.
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| MC14LC5480DT | 功能描述:IC PCM CODEC-FILTER 5V 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| MC14LC5480DW | 功能描述:IC CODEC-FILTER PCM 5V 20-SOIC W RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| MC14LC5480DWR2 | 功能描述:IC 5V PCM CODEC-FILTER 20-SOIC W RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
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