參數(shù)資料
型號: MC14LC5480SDR2
廠商: Freescale Semiconductor
文件頁數(shù): 1/24頁
文件大小: 0K
描述: IC 5V PCM CODEC-FILTER 20-SSOP
標準包裝: 1
類型: PCM 編解碼器/濾波器
數(shù)據(jù)接口: PCM 音頻接口
分辨率(位): 13 b
ADC / DAC 數(shù)量: 1 / 1
三角積分調(diào)變:
電壓 - 電源,數(shù)字: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP
包裝: 剪切帶 (CT)
其它名稱: MC14LC5480SDCT
Advance Information
5 V PCM Codec-Filter
The MC14LC5480 is a general purpose per channel PCM Codec–Filter with
pin selectable Mu–Law or A–Law companding, and is offered in 20–pin DIP,
SOG, and SSOP packages. This device performs the voice digitization and
reconstruction as well as the band limiting and smoothing required for PCM
systems. This device is designed to operate in both synchronous and
asynchronous applications and contains an on–chip precision reference
voltage.
This device has an input operational amplifier whose output is the input to the
encoder section. The encoder section immediately low–pass filters the analog
signal with an active R–C filter to eliminate very high frequency noise from being
modulated down to the passband by the switched capacitor filter. From the
active R–C filter, the analog signal is converted to a differential signal. From this
point, all analog signal processing is done differentially. This allows processing
of an analog signal that is twice the amplitude allowed by a single–ended
design, which reduces the significance of noise to both the inverted and
non–inverted signal paths. Another advantage of this differential design is that
noise injected via the power supplies is a common–mode signal that is
cancelled when the inverted and non–inverted signals are recombined. This
dramatically improves the power supply rejection ratio.
After the differential converter, a differential switched capacitor filter band–
passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized
by the differential compressing A/D converter.
The decoder accepts PCM data and expands it using a differential D/A
converter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X
compensated by a differential switched capacitor filter. The signal is then filtered
by an active R–C filter to eliminate the out–of–band energy of the switched
capacitor filter.
The MC14LC5480 PCM Codec–Filter accepts a variety of clock formats,
including Short Frame Sync, Long Frame Sync, IDL, and GCI timing
environments. This device also maintains compatibility with Motorola’s family of
Telecommunication products, including the MC14LC5472 U–Interface Trans-
ceiver, MC145474/75 S/T–Interface Transceiver, MC145532 ADPCM Trans-
coder, MC145422/26 UDLT–1, MC145421/25 UDLT–2, and MC3419/MC33120
SLIC.
The MC14LC5480 PCM Codec–Filter utilizes CMOS due to its reliable
low–power performance and proven capability for complex analog/digital VLSI
functions.
Pin for Pin Replacement for the MC145480
Single 5 V Power Supply
Typical Power Dissipation of 15 mW, Power–Down of 0.01 mW
Fully–Differential Analog Circuit Design for Lowest Noise
Transmit Band–Pass and Receive Low–Pass Filters On–Chip
Active R–C Pre–Filtering and Post–Filtering
Mu–Law and A–Law Companding by Pin Selection
On–Chip Precision Reference Voltage (1.575 V)
Push–Pull 300 Power Drivers with External Gain Adjust
MC145536EVK is the Evaluation Kit that Also Includes the MC145532
ADPCM Transcoder
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Order this document
by MC14LC5480/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MC14LC5480
DW SUFFIX
SOG PACKAGE
CASE 751D
P SUFFIX
PLASTIC DIP
CASE 738
ORDERING INFORMATION
MC14LC5480P
Plastic DIP
MC14LC5480DW
SOG Package
MC14LC5480SD
SSOP
20
1
20
1
VDD
PO-
PI
RO-
RO+
PDI
BCLKR
DR
FSR
PO+
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Mu/A
TG
TI-
TI+
VAG
MCLK
BCLKT
DT
FST
VSS
SD SUFFIX
SSOP
CASE 940C
20
1
REV 0.1
5/96
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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