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| 型號： | MC26LS30DR2 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DRIVER LINE CONFIG 16SOIC |
| 產(chǎn)品變化通告： | Product Obsolescence 14/Apr/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 驅(qū)動器 |
| 驅(qū)動器/接收器數(shù)： | 4/0 |
| 規(guī)程： | RS422，RS423 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | MC26LS30DR2OSDKR |
MC26LS30
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (EIA422A differential mode, Pin 4
p 0.8 V, 40°C tTA t 85°C, 4.75 V p VCC p 5.25 V,
VEE = Gnd, unless otherwise noted. Pin numbers refer to SO16 package only.)
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage (see Figure 1)
Differential, RL = ∞, VCC = 5.25 V
Differential, RL = 100 , VCC = 4.75 V
Offset Voltage, RL = 100
Change in Offset Voltage*, RL = 100
VOD1
VOD2
VOS
VOS
2.0
4.2
2.6
10
2.5
10
6.0
400
3.0
400
Vdc
mVdc
Vdc
mVdc
Output Current (each output)
Power Off Leakage, VCC = 0, 10 V p VO p +10 V
High Impedance Mode, VCC = 5.25 V, 10 V p VO p +10 V
Short Circuit Current (Note 2)
High Output Shorted to Pin 5 (TA = 25°C)
High Output Shorted to Pin 5 (40
°C t TA t+85°C)
Low Output Shorted to +6.0 V (TA = 25°C)
Low Output Shorted to +6.0 V (40
°C t TA t +85°C)
IOLK
IOZ
ISC
ISC+
100
150
60
50
0
95
75
+100
60
50
150
A
mA
Inputs
Low Level Voltage
High Level Voltage
Current @ Vin = 2.4 V
Current @ Vin = 15 V
Current @ Vin = 0.4 V
Current, 0
p Vin p 15 V, VCC = 0
Clamp Voltage (Iin = 12 mA)
VIL
VIH
IIH
IIHH
IIL
IIX
VIK
2.0
200
1.5
0
8.0
0
0.8
40
100
Vdc
A
Vdc
Power Supply Current (VCC = +5.25 V, Outputs Open)
(0
p Enable p VCC)
ICC
16
30
mA
TIMING CHARACTERISTICS (EIA422A differential mode, Pin 4
unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
Differential Output Rise Time (Figure 3)
tr
70
200
ns
Differential Output Fall Time (Figure 3)
tf
70
200
ns
Propagation Delay Time Input to Differential Output
Input Low to High (Figure 3)
Input High to Low (Figure 3)
tPDH
tPDL
90
200
ns
Skew Timing (Figure 3)
tPDH to tPDL for Each Driver
Max to Min tPDH Within a Package
Max to Min tPDL Within a Package
tSK1
tSK2
tSK3
9.0
2.0
ns
Enable Timing (Figure 4)
Enable to Active High Differential Output
Enable to Active Low Differential Output
Enable to 3State Output From Active High
Enable to 3State Output From Active Low
tPZH
tPZL
tPHZ
tPLZ
150
190
80
110
300
350
300
ns
1. All voltages measured with respect to Pin 5.
2. Only one output shorted at a time, for not more than 1 second.
3. Typical values established at +25
°C, VCC = +5.0 V, VEE = 5.0 V.
4. Vin switched from 0.8 to 2.0 V.
5. Imbalance is the difference between
VO2 with Vin t 0.8 V and VO2 with Vin u 2.0 V.
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