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參數(shù)資料
| 型號： | MC33110P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | ECONOLINE: RSZ/P - 1kVDC |
| 中文描述： | COMPANDER, 0.0199 MHz BAND WIDTH, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 205K |
| 代理商： | MC33110P |
MC33110
9
MOTOROLA RF/IF DEVICE DATA
Figure 24. Compressor
+
–
2.2
μ
F
12
10
Input
10 k
Iref
VCC
Rectifier
IControl
10 k
Gain
VB
8
11
9
20 k
R2
20 k
R1
1.0
μ
F
C1
Output
2.0
μ
F
4.7 k
Compressor
The compressor is an operational amplifier with a fixed
input resistor and a variable gain cell in its feedback path as
shown in Figure 24.
The amplifier output is sampled by the precision rectifier
which, in turn, supplies a DC signal (IControl), representative
of the rectifier’s AC signal, to the variable gain cell. The
reference current (Iref) is an internally generated precision
current. The effective impedance of the variable gain cell
varies with the ratio of the two currents, and decreases as
IControl ncreases, thereby providing compression. The output
is related to the input by the following equation:
Vout = 0.3162 x
√
Vin
(Equation 1)
In terms of dB levels, the relationship is:
Vout(dB) = 0.5 x Vin(dB)
(Equation 2)
where 0 dB = 100 mVrms (see Figure 2 and 4).
The inputs and output are internally biased at VB (VCC/2),
and must therefore be capacitor coupled to external circuitry.
Pin 10 input impedance is nominally 10 k
(
±
20%), and the
maximum functional input signal is shown in Figure 18. Bias
currents required by the op amp and the variable gain cell are
internally supplied. Due to clamp diodes at the input (to VCC
and ground), the input signal must be maintained between
the supply rails. If the input signal goes more than 0.5 V
above VCC or below ground, excessive currents will flow and
distortion will show up at the output.
When no AC signals are present at the input, the variable
gain cell will attempt to set such a high gain that the circuit
may be come unstable. For this reason resistors R1 and R2,
and capacitor C1 are added to provide DC stability. The pole
formed by R1, R2 and C1 should have a pole frequency no
more than 1/10th of the lowest frequency of interest. The pole
frequency is calculated from:
f
R1
x R1 R2 C3
R2
2
(Equation 3)
for the component values shown, the pole frequency is
≈
16 Hz.
Likewise, the capacitor between Pins 11 and 8 should be
selected such that, in conjunction with the input impedance at
Pin 8 (
≈
3200
,
±
20%), the resulting pole frequency is no
more than 1/10 of the lowest frequency of interest. With the
components shown, the pole frequency is < 30 Hz. This pole
frequency is calculated from:
f
1
2
x 3.2 k x C
(Equation 4)
The output of the rectifier is filtered by the capacitor at
Pin 12, which, in conjunction with an internal 10 k resistor,
provides the time constant for the attack and decay times.
Figure 14 and 16 indicate how the times vary with the
capacitor value. The attack time for the compressor is always
faster than the decay time due to the fact that the rectifier is
fed from the output rather than the input. Since the output is
initially larger than expected (immediately after the input has
increased), the external capacitor is charged more quickly
during the initial part of the time constant. When the input is
decreased, the time constant is closer to that calculated by
t = RC. If the attack and decay times are decreased by using
a smaller capacitor, performance at low frequencies will
degrade.
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