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參數(shù)資料
| 型號(hào)： | MC33128D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER MANAGEMENT CONTROLLER |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封裝： | PLASTIC, SO-16 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 173K |
| 代理商： | MC33128D |
MC33128
5
MOTOROLA ANALOG IC DEVICE DATA
OPERATING DESCRIPTION
The MC33128 is a complete power management
controller that is designed to interface the user to the system
electronics via a microprocessor.
Outputs
Three low dropout voltage regulators are provided at outputs
1, 2 and 3. Outputs 1 and 2 were contemplated for independent
powering of the systems analog and digital circuitry. This
significantly reduces the possibility of digitally generated noise
and spurious signals from coupling into the RF and analog
circuits. The low dropout characteristic of Outputs 1 and 2 is
achieved by applying a boosted battery voltage, VBB, to their
respective driver transistors. This allows the output pass
transistors to be driven into saturation when the battery voltage
approaches 3.0 V. The VBB Output appears at Pin 4 and can be
used to provide gate bias for enhancing external N channel
MOSFET switches. Excessive loading of the V
BB
output will
result in an increase in dropout voltage.
Output 4 is derived from a voltage inverting charge pump
circuit and is intended to provide the negative gate bias
required for full depletion of RF gallium arsenide MESFETs.
In personal communication system applications such as
cellular telephone, negative gate bias is usually required by
the antenna switch and power amplifier circuit blocks with a
typical combined current of less than 1.0 mA. Output 4 can
supply in excess of 2.0 mA, but there will be an increase in
dropout voltage of Outputs 1, 2 and 3.
Outputs 1, 2, 4, VBB Generator and Thermal Protection are
all enabled and disabled in unison by the Battery Saver Input,
Pin 9. The microprocessor can be programmed to
significantly extend the system battery operating time by
periodically enabling the receiver circuitry.
Output 3 provides power to the microprocessor, flash
EPROM and the system display. These blocks are enabled
by the Power Up Input, Pin 11, and disabled by the Power
Down Input, Pin 10. By having separate power up and power
down inputs, the microprocessor can store any pending
information before turning the system and then itself OFF.
This allows a controlled or graceful shutdown. Note that the
power down request is initiated by pressing the toggle switch
while the system is “ON”. This action generates a
microprocessor non–maskable interrupt that initiates the
graceful shutdown.
Battery Voltage Detection
Reverse biasing and eventual failure of the lowest
capacity cell in the battery pack can occur if the system is
accidentally left on for an extended time period. To prevent
this condition the following circuit blocks were incorporated.
A means for low battery detection is accomplished by
using the Reference Output, Pin 12, in conjunction with the
microprocessor’s analog to digital converter input. A
microprocessor output (LBO) can be designated to flash a
display enunciator when a low battery condition exists. The
Reference Output is 1.5 V
±
2.7% and is capable of sourcing
in excess of 10 mA.
The Power Up Reset Output, Pin 13, is designed to hold
the microprocessor reset input low until the voltage at Output 3
rises above 2.66 V. This feature prevents the microprocessor
from hanging or writing invalid information into its memory
during power up. Notice that the output of the MPU Power Up
Reset comparator also drives the base of transistor QPD. If
Output 3 should fall below 2.6 V, due to an overload or a low
battery condition, the comparator will drive QPD “ON”,
causing its collector to pull high on the Power Down Input,
immediately forcing the system into standby mode.
Externally pulling down on Pin 13, base of QPD, will also force
the system into standby mode.
A redundant Low Battery Shutdown circuit is included.
This circuit directly monitors the battery voltage and also
forces the system into standby mode when the battery
voltage falls below 2.4 V. To test the functionality of this
circuit, the high state signal generated by transistor QPD must
be clamped low, to prevent resetting the ON/OFF Latch. An
external short or a pull–down, capable of sinking 2.0 mA at
less than 0.8 V, must be connected to Pin 10.
A Battery Latch circuit is designed into the IC to prevent
the system from turning on when the batteries are inserted
into the finished product. This feature is useful for the end
customer as well as the equipment manufacturer. Upon initial
application of battery voltage, the lower comparator (0.7 V
threshold) forces the Battery Latch into a reset state with its
“Q” output low. This in turn triggers a reset of the ON/OFF
Latch via the OR gate and also locks out the set signal
present at the upper input of the AND gate. As the voltage at
Pin 11 rises above (VCC – 1.5 V), the set signal disappears,
leaving the state of the ON/OFF Latch unchanged (reset).
When the voltage at Pin 11 rises above (VCC –1.0 V), the
upper comparator forces the Battery Latch into a set state
causing its “Q” output to go high. This allows the AND gate
and the ON/OFF Latch to receive a set signal from Pin 11.
The initial Battery Latch lockout time is controlled by the
internal 20 k
resistor and the external 0.1
μ
F capacitor.
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| MC33129 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:High Performance Current Mode Controllers |
| MC33129D | 制造商:Motorola Inc 功能描述: |
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