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| 型號： | MC33143DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | DUAL HIGH-SIDE SWITCH |
| 中文描述： | 6 A 2 CHANNEL, BUF OR INV BASED PRPHL DRVR, PDSO24 |
| 封裝： | PLASTIC, SOP-24 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 162K |
| 代理商： | MC33143DW |
MC33143
5
MOTOROLA ANALOG IC DEVICE DATA
Figure 2. Output Response Waveform
VPwr – 3.0 V
50%
2.0 V
VPwr
tdlh
tdhl
tSRf
tSRr
0 V
5.0 V
0 V
IN1–2
OUT1–2
PIN FUNCTION DESCRIPTION
Pin
Symbol
Description
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á
á
áááááááááááááááááááááááááááááááá
áá
áá
CEN
1, 12
á
á
áááá
áááá
Chip Enable (CEN) input pin, when low, disables both outputs (OUT1 and OUT2) and places the device
in a “sleep mode” reducing the bias current required from VDD and VPwr. A falling edge of CEN causes
OUT1 and OUT2 to rapidly turn OFF. A falling edge of CEN should precede any VDD shutdown to allow
time OUT1 and OUT2 to be disabled. When CEN is low, INTerrupt (INT) and STATus 1 and 2 (STAT1–2)
will be tri–stated (high impedance). The CEN pin can also be used for power–on reset and under
voltage lockout to disable the outputs for power supply voltages less than 4.5 V. CEN is a dependent
input from the system microcontroller unit (MCU) or some other integrated circuit. It has an internal
pull–up resistor to VDD affording a floating pin to be interpreted as a logic high. Rpull–up is greater than
50 k
. If used externally, this pin should be connected to VDD.
IN1, IN2
á
á
floating input pin to be conservatively interpreted as a logic low, turning Off the output. An unused input
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áááááááááááááááááááááááá
á
á
INput 1 and INput 2 (IN1 and IN2) respectively determine the state of the corresponding output drivers
(OUT1 and OUT2) under normal operating conditions. When an input is high, it’s corresponding output
2
3, 10
STAT1. STAT2
The STATus pins (STAT1–2) respectively indicate the presence of faults on OUT1–2. STAT1–2 will be
logic high during normal operation. A logic low will occur whenever an Open Load, Short–to–Ground,
Short–to–Supply (Battery), Thermal Limit, or Overvoltage Shutdown fault condition is experienced on a
corresponding output. STAT1–2 are both active low digital drivers. A 10 k
resistor between STAT1–2
and the system CPU may improve a Failure Mode Evaluation Analysis (FMEA) score if STAT1–2 are
externally shorted to VPwr. If unused, this pin should be left connected.
4, 9, 16,
21
VPwr
These pins are connected to the supply and provide load current to the DMOS outputs, are used
pumping the DMOS gates, and for Overvoltage shutdown detection of the DMOS. The DMOS outputs
will turn ON with 5.5 to 24 V applied to VPwr. VPwr is limited to –1.5 V for a maximum duration of
250 ms. A 10 nF de–coupling cap is recommended to be used from VPwr to Ground.
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á
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á
áááááááááááááááááááááááááááááááááá
á
á
á
á
áááááááááááááááááááááááááááááááá
áá
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13, 24
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5, 6, 7, 8,
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áá
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áá
áá
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áááááááááááááááááááááááááá
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Gnd
áááááááááááááááááááááááá
áááááááááááááááááááááááá
recommended from VDD to Gnd.
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áááá
áááá
áááá
á
These eight pins constitute the circuits ground (Gnd) and also provide heatsinking for the DMOS output
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á
áááááááááááááááááááááááá
áááááááááááááááááááááááá
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áááááááááááááááááááááááá
á
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OUT1, OUT2
á
á
á
á
These pins are connected internally to the DMOS output transistors which source current into the
and protection, thermal limit detection and protection, ON open load and or short to supply (battery)
provide dV/dt noise filtering.
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