參數(shù)資料
型號: MC33201VDR2G
廠商: ON Semiconductor
文件頁數(shù): 18/18頁
文件大小: 0K
描述: IC OPAMP SGL R-R LV 8-SOIC
標準包裝: 2,500
放大器類型: 通用
電路數(shù): 1
輸出類型: 滿擺幅
轉換速率: 1 V/µs
增益帶寬積: 2.2MHz
電流 - 輸入偏壓: 80nA
電壓 - 輸入偏移: 6000µV
電流 - 電源: 900µA
電流 - 輸出 / 通道: 80mA
電壓 - 電源,單路/雙路(±): 1.8 V ~ 12 V,±0.9 V ~ 6 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOICN
包裝: 帶卷 (TR)
MC33201, MC33202, MC33204, NCV33202, NCV33204
http://onsemi.com
9
DETAILED OPERATING DESCRIPTION
General Information
The MC33201/2/4 family of operational amplifiers are
unique in their ability to swing railtorail on both the input
and the output with a completely bipolar design. This offers
low noise, high output current capability and a wide
common mode input voltage range even with low supply
voltages. Operation is guaranteed over an extended
temperature range and at supply voltages of 2.0 V, 3.3 V and
5.0 V and ground.
Since the common mode input voltage range extends from
VCC to VEE, it can be operated with either single or split
voltage supplies. The MC33201/2/4 are guaranteed not to
latch or phase reverse over the entire common mode range,
however, the inputs should not be allowed to exceed
maximum ratings.
Circuit Information
Railtorail performance is achieved at the input of the
amplifiers by using parallel NPNPNP differential input
stages. When the inputs are within 800 mV of the negative
rail, the PNP stage is on. When the inputs are more than 800
mV greater than VEE, the NPN stage is on. This switching of
input pairs will cause a reversal of input bias currents (see
Figure 6). Also, slight differences in offset voltage may be
noted between the NPN and PNP pairs. Crosscoupling
techniques have been used to keep this change to a minimum.
In addition to its railtorail performance, the output stage
is current boosted to provide 80 mA of output current,
enabling the op amp to drive 600
W loads. Because of this
high output current capability, care should be taken not to
exceed the 150
°C maximum junction temperature.
O
,OUTPUT
VOL
TAGE
(50
mV/DIV)
V
t, TIME (10
ms/DIV)
Figure 26. Noninverting Amplifier Slew Rate
Figure 27. Small Signal Transient Response
t, TIME (5.0
ms/DIV)
Figure 28. Large Signal Transient Response
VCC = +6.0 V
VEE = -6.0 V
RL = 600 W
CL = 100 pF
TA = 25°C
O
,OUTPUT
VOL
TAGE
(2.0
mV/DIV)
VCC = +6.0 V
VEE = -6.0 V
RL = 600 W
CL = 100 pF
AV = 1.0
TA = 25°C
V
VCC = +6.0 V
VEE = -6.0 V
RL = 600 W
CL = 100 pF
TA = 25°C
t, TIME (10
ms/DIV)
O
,OUTPUT
VOL
TAGE
(2.0
V/DIV)
V
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will selfalign when subjected to a
solder reflow process.
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