參數(shù)資料
型號: MC33291
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Eight Output Switch with Serial Peripheral Interface I/O(帶SPI接口的八輸出開關(guān))
中文描述: 8個(gè)串行外圍接口的I / O(帶的SPI接口的八輸出開關(guān)輸出開關(guān))
文件頁數(shù): 15/24頁
文件大?。?/td> 633K
代理商: MC33291
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33291
15
FUNCTIONAL PIN DESCRIPTION
CS Pin
The 33291 receives its MCU communication through the CS
pin. Whenever this pin is in a logic low state, data can be
transferred from the MCU to the 33291 by way of the SI pin and
from the 33291 to the MCU through the SO pin. Clocked-in data
from the MCU is transferred from the 33291 Shift register and
latched into the power outputs on the rising edge of the CS
signal. On the falling edge of the CS signal, drain status
information is transferred from the power outputs then loaded
into the Shift register of the device. The CS pin also controls the
output driver of the serial output (SO) pin. Whenever the CS pin
goes to a logic low state, the SO pin output driver is enabled
allowing information to be transferred from the 33291 to the
MCU. To avoid data corruption or the generation of spurious
data, it is essential the high-to-low transition of the CS signal
occur only when SCLK is in a logic low state.
SCLK Pin
The system clock (SCLK) pin clocks the internal shift
registers of the 33291. The serial input (SI) pin accepts data into
the Input Shift register on the falling edge of the SCLK signal
while the serial output (SO) pin shifts data information out of the
SO line driver on the rising edge of the SCLK signal. False
clocking of the Shift register must be avoided to guarantee
validity of data. It is essential the SCLK pin be in a logic low
state whenever the chip select bar (CS) pin makes any
transition. For this reason, it is recommended, though not
absolutely necessary, the SCLK pin be kept in a low logic state
as long as the device is not accessed (CS in logic high state).
When CS is in a logic high state, signals at the SCLK and SI
pins are ignored and SO is tri-stated (high impedance). See the
Data Transfer Timing diagram in Figure 16.
SI Pin
This pin is for the input of serial instruction (SI) data. SI is
read on the falling edge of SCLK. A logic high state present on
this pin when the SCLK signal rises will program a specific
output OFF. In turn, the pin turns OFF the specific output on the
rising edge of the CS signal. Conversely, a logic low state
present on the SI pin will program the output ON, In turn, the pin
turns ON the specific output on the rising edge of the CS signal.
To program the eight outputs of the 33291 ON or OFF, an 8-
bit serial stream of data is required to be synchronously entered
into the SI pin starting with Output 7, followed by Output 6,
Output 5, and so on, to Output 0. Referring to Figure 16, the DO
bit is the most significant bit (MSB) corresponding to Output 7.
For each rise of the SCLK signal, with CS held in a logic low
state, a data-bit instruction (ON or OFF) is synchronously
loaded into the Shift register per the data-bit SI state. The Shift
register is full after eight bits of information have been entered.
To preserve data integrity, care should be taken to not transition
SI as SCLK transitions from a low-to-high logic state.
SO Pin
The serial output (SO) pin is the
tri-stateable
output from the
Shift register. The SO pin remains in a high impedance state
until the CS pin goes to a logic low state. The SO data reports
the drain status, either high or low relative to the previous
command word. The SO pin changes state on the rising edge
of SCLK and reads out on the falling edge of SCLK. When an
output is OFF and not faulted, the corresponding SO data-bit is
a high state. When an output is ON, and there is no fault, the
corresponding data-bit on the SO pin will be a low logic state.
The SI/SO shifting of data follows a first-in-first-out (FIFO)
protocol with both input and output words transferring the MSB
first. Referring to Figure 16, the DO
bit is the MSB
corresponding to Output 7 relative to the previous command
word. The SO pin is not affected by the status of the Reset pin.
RST Pin
The 33291 reset (RST) pin is active low. It is used to clear the
SPI Shift register. In doing so, all output switches are set at
OFF. The device situated in the same system with an MCU, the
MCU retains the Reset pin of the device in a logic low state.
Retention ensures all outputs to be OFF until both the V
DD
and
V
PWR
pin voltages are adequate for predictable operation.
Retention of the device Reset pin takes place only upon initial
system power up. After the 33291 is reset, the MCU is ready to
assert system control with all output switches initially OFF.
If the V
PWR
pin of the 33291 experiences a low voltage,
following normal operation, the MCU should pull the Reset pin
low to shutdown the outputs and clear the input data register.
The Reset pin is active low and has an internal pull-down
incorporated, insuring operational predictability should the
external pull-down of the MCU open circuit. The internal pull-
down is only 25 μA, affording safe and easy interfacing to the
MCU. The Reset pin of the 33291 should be pulled to a logic low
state for a duration of at least 250 ns, ensuring reliable a reset.
Figure 15. Power ON Reset
A simple power ON reset delay of the system can be
programmed through the use of an RC network comprised of a
shunt capacitor from the Reset pin to Ground and a resistor to
V
DD
, illustrated in Figure 15. Care should be exercised ensuring
proper discharge of the capacitor. Careful attention eliminates
adverse delay of the Reset and damage of the MCU if it pulls
the Reset line low, thereby accomplishing initialization for turn
+
V
DD
R
DLY
C
DLY
Reset
20 μA
Reset
MCU
33291L
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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