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參數(shù)資料
| 型號(hào)： | MC33304P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | RAIL-TO-RAIL SLEEPMODE OPERATIONAL AMPLIFIER |
| 中文描述： | QUAD OP-AMP, 13000 uV OFFSET-MAX, 2.2 MHz BAND WIDTH, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 361K |
| 代理商： | MC33304P |
MC33304
3
MOTOROLA ANALOG IC DEVICE DATA
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5.0 V, VEE = Gnd, TA = 25
°
C, unless otherwise noted.)
Characteristic
Unit
Max
Typ
Min
Symbol
Output Voltage Swing (VID =
±
0.2 V)
Sleepmode
VCC = +5.0 V, VEE = 0 V, RL = 1.0 M
VCC = 0 V, VEE = –5.0 V, RL = 1.0 M
VCC = +2.0 V, VEE = 0 V, RL = 1.0 M
VCC = 0 V, VEE = –2.0 V, RL = 1.0 M
Awakemode
VCC = +5.0 V, VEE = 0 V, RL = 600
VCC = 0 V, VEE = –5.0 V, RL = 600
VCC = +2.0 V, VEE = 0 V, RL = 600
VCC = 0 V, VEE = –2.0 V, RL = 600
VCC = +2.5 V, VEE = –2.5 V, RL = 600
VCC = +2.5 V, VEE = –2.5 V, RL = 600
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
4.90
–
1.90
–
4.75
–
1.85
–
–
–
4.97
–4.96
1.98
–1.97
4.86
–4.85
1.91
–1.90
2.41
–2.40
–
–4.90
–
–1.90
–
–4.75
–
–1.85
–
–
V
Common Mode Rejection Ratio
CMRR
60
90
–
dB
Power Supply Current (per Amplifier)
Sleepmode
VCC = +2.0 V, VEE = 0 V
VCC = +2.5 V, VEE = –2.5 V
TA = +25
°
C
TA = +25
°
C
TA = –40
°
to +105
°
C
TA = +25
°
C
VCC = +12 V, VEE = 0 V
Awakemode
VCC = +2.5 V, VEE = –2.5 V
TA = +25
°
C
TA = –40
°
to +105
°
C
ID
–
–
–
–
–
–
85
110
–
125
1200
–
–
140
150
–
1625
1750
μ
A
Thermal Resistance
SOIC
Plastic DIP
θ
JA
–
–
145
75
–
–
°
C/W
AC ELECTRICAL CHARACTERISTICS
(VCC = +6.0 V, VEE = –6.0 V, RL = 600
, TA = 25
°
C, unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
Slew Rate (VCC = +2.5 V, VEE = –2.5 V, AV = +1.0) (Note 6)
Awakemode
SR
0.5
0.89
–
V/
μ
s
Gain Bandwidth Product (f = 100 kHz)
Awakemode
GBW
–
2.2
–
MHz
Gain Margin (CL = 0 pF)
Awakemode
Sleepmode (RL = 1.0 k
)
Phase Margin (RL = 1.0 k
, VO = 0 V, CL = 0 pF)
Awakemode
Sleepmode
Am
–
–
6.0
9.0
–
–
dB
φ
m
–
–
40
60
–
–
Deg
Sleepmode to Awakemode Transition Time
RL = 600
RL = 10 k
ttr1
–
–
4.0
12
–
–
μ
sec
Awakemode to Sleepmode Transition Time
ttr2
CS
–
1.5
–
sec
Channel Separation (f = 1.0 kHz)
Awakemode
–
100
–
dB
NOTES:
1.The differential input voltage of each amplifier is limited by two internal diodes. The diodes are connected across the inputs in parallel and opposite to
each other. For more differential input voltage range, use current limiting resistors in series with the input pins.
2.The common–mode input voltage range of each amplifier is limited by diodes connected from the inputs to both power supply rails. Therefore, the
voltage on either input must not exceed supply rail by more than
±
500 mV.
3.Simultaneous short circuits of two or more amplifiers to the positive or negative rail can exceed the power dissipation ratings and cause eventual
failure of the device.
4.Rail–to–rail performance is achieved at the input of the amplifier by using parallel NPN–PNP differential stages. When the inputs are near the
negative rail (VEE < VCM < 800 mV), the PNP stage is on. When the inputs are above 800 mV (i.e. 800 mV < VCM < VCC), the NPN stage is on.
This switching of the input pairs will cause a reversal of input bias current. Slight changes in the input offset voltage will be noted between the NPN
and PNP pairs. Cross–coupling techniques have been used to keep this change to a minimum.
5.Power dissipation must be considered to ensure maximum junction (TJ) is not exceeded. (See Figure 2)
6.When connected as a voltage follower and used in transient conditions, a current limiting resistor may be needed between the output and the
inverting input. This is because of the back to back diodes clamped across the inputs. The value of this resistor should be between 1.0 k
and
10 k
. If the amplifier does not become slew rate limited and is processing low frequency waveforms, then no resistor would be necessary.
(The output could be tied directly to the negative input.)
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