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參數(shù)資料
| 型號： | MC33560DTBR2 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE PWR MANAGMT 24TSSOP |
| 產(chǎn)品變化通告： | Product Obsolescence 11/Feb/2009 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 24-TSSOP（0.220"，5.60mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | MC33560DTBR2OSDKR |
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MC33560
http://onsemi.com
16
First, determine the maximum current that the application
requires to supply to the card (ICCmax, on the yaxis)
Then, select one curve that crosses the selected ICCmax
level. The curve is associated with an inductance value
(22
mH, 47 mH, or 100 mH).
Finally, use the intersection of the curve and the ICCmax
level to find the Rlim value on the xaxis.
Good starting values are : L1 = 47
mH; Rlim = 0.5 W
Note also that, for a high inductance value (100
mH), the
filtering capacitor is generally charged before inductance
current reaches current limitation, while for alow inductance
value, the current limitation is activated after a few converter
cycles.
Battery Requirements: Having determined the L1 and
Rlim values, the maximum current drawn from the battery
When the application is powered by a single 3.0 V battery,
special care has to be taken to extend its lifetime. When
lithium batteries approach the endoflife, their internal
resistance
increases,
while
voltage
decreases.
This
phenomenon can prevent the startup of the DCDC
converter if the current limiting is set too high, because of the
filtering capacitor charging current.
CLOCK GENERATOR
The primary purpose of the clock generator module is to
match the smartcard operating frequency to the system
frequency. The source frequency can be provided to
ASYCLKIN by the microcontroller itself or from an
external oscillator circuit.
In programming mode (RDYMOD=L and CS asserted
low) the three input variables PWRON, I/O and RESET are
used to configure the two output variables CRDVCC and
CRDCLK as described in Table 3. This circuit setup is
latched during the positive transition of CS.
Furthermore, in asynchronous mode the system clock
frequency ASYCLKIN can be divided by a factor of 1, 2
or 4. The circuit controls the frequency commutation to
guarantee that the card clock signal remains free from spikes
and glitches. In addition, this circuit ensures that CRDCLK
signal pulses will not be shorter than the shortest and/or
longer than the longest of the clock signals present before
and after programming changes.
The INVOUT output is provided to drive other circuits
without additional load to the microprocessor quartz
oscillator. It can also be used to build a local RC oscillator.
This driver has been optimized for low consumption; it has
no hysteresis, and input levels are not symmetrical. If the
ASYCLKIN pin is connected to a sine wave, the duty cycle
will not always be 50% at INVOUT.
CLOCK GENERATOR OPERATING PRINCIPLES
Synchronous Clock: This clock is used mainly for
memory cards. It can also be used for asynchronous
(microprocessor) cards, allowing the use of two different
clock sources. The status of SYNCLK is latched at
CRDCLK when CS goes high, so that data (the I/O pin) and
clock are always consistent at the card connector, whatever
the CS status is. When using the synchronous clock, the
clock output becomes active only when the MC33560 is
selected with CS.
Asynchronous Clock: This clock is used mainly for
microprocessor cards. When applied, the clock output
remains active even when the MC33560 is not selected with
CS, in order to keep the microprocessor running and avoid
an unwanted reset. The ASYCLKIN signal is buffered at the
INVOUT pin, so that several MC33560 systems can use the
same clock with one load only.
Depending on programming, the frequency is fed directly,
or divided by 2 or by 4 to the CRDCLK pin. If the duty cycle
of the applied clock signal is not exactly symmetrical, it is
recommended that the clock signal be divided by two or four
to guarantee 50% duty cycle.
Clock
Signal
Synchronization
and
Consistency
(Figure 29). The clock divider includes synchronization
logic that controls the switch from synchronous clock to
asynchronous (and viceversa), from any division ratio to
any other ratio, during CS changes and at powerup. The
synchronization logic guarantees that each clock cycle on
the CRDCLK pin is finished before changing clock
selection (and has always the adequate duration), regardless
of the moment the programming is changed.
At powerup, when ASYCLKIN is selected, the clock
signal at the CRDCLK pin has an entire length, according
to the selected divide ratio, whatever the ASYCLKIN signal
is versus the internal sequencer timing.
Figure 23. Clock Generator Functional Block
IO
RESET
SYNCLK
ASYCLKIN
INVOUT
CARDENABLE
SYNCHRONISA
TION
LOGIC
SELECT
OR
SELECTOR
LATCH
SYNCHRO
LATCH
CRDVCC
CRDCLK
SEQ3
PROGRAM
2
B
LATCH
2
B
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC33560DTBR2G | 功能描述:輸入/輸出控制器接口集成電路 3V/5V Smartcard Power Management RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| MC33560DW | 功能描述:輸入/輸出控制器接口集成電路 3V/5V Smartcard RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| MC33560DWR2 | 功能描述:輸入/輸出控制器接口集成電路 3V/5V Smartcard RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| MC33560DWR2G | 功能描述:輸入/輸出控制器接口集成電路 3V/5V Smartcard Power Management RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| MC33565D | 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 200mA w/Sleep RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
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