OPERATIONAL MODES In the recessive state th" />
參數(shù)資料
型號(hào)： MC33742DW
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 38/71頁(yè)
文件大?。?/td> 0K
描述： IC SYSTEM BASE W/LIN 28-SOIC
標(biāo)準(zhǔn)包裝： 26
應(yīng)用： 自動(dòng)
接口： SPI
電源電壓： 5.5 V ~ 18 V
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 管件
安裝類型： 表面貼裝
配用： KIT33742DWEVB-ND - KIT FOR 33742 SBC WITH EHSCAN
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
33742
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
In the recessive state the failure detection to GND or VSUP is possible. However, it is impossible to distinguish which bus line,
CANL or CANH, is shorted to GND or VSUP. In the dominant state, the complete diagnostic is possible once the driver is turned
on.
CAN BUS FAILURE REPORTING
CANL bus line failures (for example, CANL short to GND) is reported in the SPI register TIM1/2. CANH bus line (for example,
CANH short to VSUP) is reported in the LPC register.
In addition CAN-F and CAN-UF bits in the CAN register indicate that a CAN bus failure has been detected.
NON-IDENTIFIED AND FULLY IDENTIFIED BUS FAILURES
As indicated in Table 11, page 42, when the bus is in a recessive state it is possible to detect an error condition; however, is
it not possible to fully identify the specific error. This is called “non-identified” or “under-acquisition” bus failure. If there is no
communication (i.e., bus idle), it is still possible to warn the MCU that the SBC has started to detect a bus failure.
In the CAN register, bits D2 and D1 (CAN-F and CAN-UF, respectively) are used to signal bus failure. Bit D2 reports a bus
failure and bit D1 indicates if the failure is identified or not (bit D1 is set to logic [1} if the error is not identified).
When the detection mechanism is fully operating any bus error will be detected and reported in the TIM1/2 and LPC registers
and bit D1 will be reset to logic [0].
NUMBER OF SAMPLES FOR PROPER FAILURE DETECTION
The failure detector requires at least one cycle of recessive and dominant state to properly recognize the bus failure. The error
will be fully detected after five cycles of recessive-dominant states. As long as the failure detection circuitry has not detected the
same error for five recessive-dominant cycles, the bit “non-identified failure” (CAN-UF) will be set.
RXD PERMANENT RECESSIVE FAILURE
The purpose of this detection mechanism is to diagnose an external hardware failure at the RXD output pin and to ensure that
a permanent failure at the RXD pin does not disturb network communication.In the event RXD is shorted to a permanent high
level signal (i.e., 5.0 V), the CAN protocol module within the MCU cannot receive any incoming message. Additionally, the CAN
protocol module cannot distinguish the bus idle state and could start communication at any time. To prevent this, an RXD failure
detection, as illustrated in Figure 25 and explained below, is necessary.
Figure 25. RXD Path and RXD Permanent Recessive Detection Principle
RXD FAILURE DETECTION
The SBC senses the RXD output voltage at each LOW-to-HIGH transition of the differential receiver. Excluding internal
propagation delay, RXD output should be LOW when the differential receiver is LOW. In the event RXD is shorted to 5.0 V (e.g.,
to VDD), RXD will be tied to a high level and the RXD short to 5.0 V can be detected at the next LOW-to-HIGH transition of the
differential receiver. Compete detection requires three samples.
When the error is detected, an error flag is latched and the CAN driver is disabled. The error is reported through the SPI
register LPC, bit RXPR.
CANL
Diff Output
RXD Output
RXD Short to V1
Prop Delay
RXD Flag
RXD Flag Latched
Sampling
Sampling Sampling
Note The RXD Flag is neither the RXPR bit in the LPC register, nor the CANF bit in the INTR register.
CANH
CANL
Diff
V2
RXD Sense
RXD
TXD
60
V2
Logic
Diag
2.0 V
Driver
GND
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