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參數(shù)資料
| 型號(hào)： | MC33886 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 5.0 A H-Bridge(5.0A H橋接器) |
| 中文描述： | 5.0的H -橋（5.0AH橋接器） |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 637K |
| 代理商： | MC33886 |
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33886
7
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 5.0 V
≤
V+
≤
28 V and -40
°
C
≤
T
A
≤
125
°
C unless otherwise noted. Typical values noted
reflect the approximate parameter mean at T
A
= 25
°
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency (Note 20)
f
PWM
–
–
10
kHz
Maximum Switching Frequency During Active Current Limiting (Note 21)
f
MAX
–
–
20
kHz
Output ON Delay (Note 22)
V+ = 14 V
t
d
(ON)
–
–
18
μ
s
Output OFF Delay (Note 22)
V+ = 14 V
t
d(OFF)
–
–
18
μ
s
Output Rise and Fall Time (Note 23)
V+ = 14 V, I
OUT
= 3.0 A
t
f
, t
r
2.0
5.0
8.0
μ
s
Output Latch-OFF Time
t
a
15
20.5
26
μ
s
Output Blanking Time
t
b
12
16.5
21
μ
s
Output FET Body Diode Reverse Recovery Time (Note 24)
t
rr
100
–
–
ns
Disable Delay Time (Note 25)
t
d(disable)
–
–
8.0
μ
s
Short Circuit/Overtemperature Turn-
OFF
Time (Note 26)
t
FAULT
–
4.0
–
μ
s
Power-OFF Delay Time
t
pod
–
1.0
5.0
ms
Notes
20.
The outputs can be PWM controlled from an external source. This is typically done by holding one input high while applying a PWM pulse
train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching frequency. Refer
to Typical Switching Waveforms,
Figures 11
through
18
, pp. 12–13.
The Maximum Switching Frequency during active current limiting is internally implemented. The internal control produces a constant OFF-
time PWM of the output. The output load current effects the Maximum Switching Frequency.
Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition
direction) of the OUT1 or OUT2 signal. If the output is transitioning High-to-Low, the delay is from the midpoint of the input signal to the 90%
point of the output response signal. If the output is transitioning Low-to-High, the delay is from the midpoint of the input signal to the 10%
point of the output response signal. See
Figure 2
, page 8.
Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See
Figure 4
, page 8.
Parameter is guaranteed by design but not production tested.
Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See
Figure 3
,
page 8.
Increasing currents will become limited at I
LIM
. Hard shorts will breach the I
SCH
or I
SCL
limit, forcing the output into an immediate tri-state
latch-OFF. See
Figures 6
and
7
, page 9. Active current limiting will cause junction temperatures to rise. A junction temperature above 160
°
C
will cause the active current limiting to progressively "fold back" (or decrease) to 2.5 A typical at 175
°
C where thermal latch-OFF will occur.
See
Figure 5
, page 8.
21.
22.
23.
24.
25.
26.
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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