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參數(shù)資料
| 型號： | MC38HC705J2 |
| 廠商： | Motorola, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RTS Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 3.3V; Power: 2W; Assembly; High Power Density; Optional Continuous Short Circuit Protected; Efficiency to 85% |
| 中文描述： | M68HC05系列系列8位微控制器單元 |
| 文件頁數(shù)： | 16/78頁 |
| 文件大?。?/td> | 427K |
| 代理商： | MC38HC705J2 |
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MC68HC705J2
PARALLEL I/O
MOTOROLA
3-1
SECTION 3
PARALLEL I/O
This section describes the two bidirectional I/O ports.
3.1 I/O Port Function
The 14 I/O pins form two I/O ports. Each I/O pin is programmable as an input or
an output. The contents of a port data direction register (DDR) determine the
data direction for the port. Writing a 1 to a DDR bit enables the output buffer for
the associated port pin; a 0 disables the output buffer. A reset initializes all
implemented DDR bits to 0, configuring all I/O pins as inputs.
NOTE
Connect any unused inputs and I/O pins to an appropriate logical
level, either V
DD
or V
SS
. Although the I/O ports do not require
termination for proper operation, termination reduces the
possibility of electrostatic damage.
A reset does not initialize the two port data registers. The port data registers for
ports A and B are at addresses $0000 and $0001. To avoid undefined levels,
write the data registers before writing the data direction registers.
With an I/O port pin programmed as an output, reading the pin actually reads
the value of the output data latch and not the voltage on the pin itself. When a
pin is programmed as an input, reading the port bit reads the voltage level on
the I/O pin. The output data latch can always be written, regardless of the state
of its DDR bit. Refer to Figure 3-1 for typical port circuitry, and to Table 3-1 for a
summary of I/O pin functions.
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