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參數(shù)資料
| 型號： | MC44462B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 畫面疊加 |
| 英文描述： | Y-C PICTURE-IN-PICTURE (PIP) CONTROLLER |
| 中文描述： | PICTURE-IN-PICTURE IC, PDIP56 |
| 封裝： | SHRINK, PLASTIC, DIP-56 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 183K |
| 代理商： | MC44462B |
MC44462
5
MOTOROLA ANALOG IC DEVICE DATA
I2C REGISTER DESCRIPTIONS
Base write address = 24h
Base read address = 25h
Read Register
There are two active bits in the single read byte available
from the MC44462 as follows:
Write Vertical Indicator (WVI0) – D7
When 0 indicates that the write operation specified by the
last I2C command has been completed.
PIP Sync Detect Bit (PSD0) – D1
When 0 indicates that the PIP video H pulses are present
and the horizontal timebase oscillator is within acceptable
limits.
Write Registers
Read Start Position/Write Start Position Registers
Sub–address = 00h
Write Raster Position Start Bits (WPS0–2) – D0–D2
Establishes the horizontal beginning of the PIP and its
black level measurement gate. This beginning may be varied
by approximately 3.0
μ
s. The position of this pulse may be
observed through the Multi Test Pin 30 (See Test Mode
Register Sub–address 03h).
Read Raster Position Bits (RPS0–3) – D4–D7
Establishes the clamp gate position for the black level
reference for the main picture. This position may be varied by
approximately 5.0
μ
s. The position of this pulse may be
observed through the Multi Test Pin 30 (See Test Mode
Register Sub–address 03h).
Pip Switch Delay/Vertical Filter Register
Sub–address = 01h
PIP Switch Delay Bits (PSD0–3) – D0–D3
Delays the start of PIP on time relative to the PIP picture.
These bits are used to center the PIP border and PIP picture
in the horizontal direction.
Vertical Filter Bit (VFON) – D4
When the filter is activated (VFON = 1) a three line
weighted average is taken to provide the data stored in the
field memory.
Border Color Register
Sub–address = 02h
Border Color Bits (BC0–2) – D0–D2
These Bits control the color of the border. Note that when
using one of the saturated border colors it is possible to get
objectionable dot crawl at the edge of the border in some TVs
unless appropriate comb filtering is used in the TV circuitry.
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Test Mode/Main Vertical and Horizontal Polarity Register
Sub–address = 03h
Internal Test Mode Register (ITM0–2) – D0–D2
Sets the Multi Test Pin output to provide one of several
internal signals for test and production alignment. Also
controls the test memory address counter.
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Main vertical polarity select bit (MVP0) – D6
Selects polarity of active level of vertical reference input.
0 = positive going, 1 = negative going.
Main horizontal polarity select bit (MHP0) – D7
Selects polarity of active level of horizontal reference
input. 0 = positive going, 1 = negative going.
PIP Freeze/PIP Size/Main and PIP Video Source Register
Sub–address = 04h
PIP Freeze Bit (STIL0) – D4
When set to one, the most recently received field is
continuously displayed until the freeze bit is cleared.
PIP Size Bit (PSI90) – D5
Switches the PIP size between 1/16 main size (when 0)
and 1/9 main size (when 1).
Video Type Select Bit (YCPSEL) – D6
Selects which video type will be applied to the PIP input.
PIP Video Source Select Bit (PSEL0) – D7
Selects which composite video input will be applied to the
video decoder to provide the PIP video in CV mode.
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0
0
1
CV1 Input to PIP
CV1 Input to PIP
CV2 Input to PIP
PIP On/PIP Blank Register
Sub–address = 05h
PIP On Bit (PON0) – D0
When on (1) turns the PIP on.
PIP Blanking Bit (PBL0) – D4
When on (1) sets the PIP to black. If the PIP is off, then it
will be black if it is turned on. Overrides all other settings of
the PIP control.
PIP X Position Register
Sub–address = 06h
X Position Bits (XPS0–5) – D0–D5
Moves the PIP start position from the left to the right
edge of the display in 64 steps. There is protection circuitry
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| MC44463 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:REPLAY AND MULTIPLE PICTURE-IN-PICTURE (PIP) CONTROLLER |
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