參數(shù)資料
型號(hào)： MC44463
廠商： Motorola, Inc.
英文描述： REPLAY AND MULTIPLE PICTURE-IN-PICTURE (PIP) CONTROLLER
中文描述： 重播和多重畫中畫，畫中畫（PIP）控制器
文件頁數(shù)： 6/8頁
文件大小： 199K
代理商： MC44463
MC44463
6
MOTOROLA ANALOG IC DEVICE DATA
PIP On/PIP Blank Register
Sub–address = 05h
PIP On Bits (PON0–3) – D4–D3
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PIP Blanking Bits (PBL0–3) – D4–D7
When on (1) sets the corresponding PIP to black. If the
individual PIP is off, then it will be black when it is turned on.
PON (3:0)
1/16 Size
1/9 Size
0000
No PIP
No PIP
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0001
Top = On
Top = On
0010
2nd from Top = On
2nd from Top = On
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0100
3rd from Top = On
3rd from Top = On
1000
4th from Top = On
3rd from Top = On
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PIP X Position Register
Sub–address = 06h
X Position Bits (XPS0–5) – D0–D5
Moves the PIP start position from the left to the right
edge of the display in 64 steps. There is protection circuitry
to prevent the PIP from interfering with the main picture
sync pulses.
PIP Y Position Register
Sub–address = 07h
Y Position Bits (YPS0–5) – D0–D5
Moves the PIP start position from the top to the bottom
edge of the display in 64 steps. There is protection circuitry to
prevent the PIP from interfering with the main picture sync
pulses.
PIP Chroma Level Register
Sub–address = 08h
Chroma (C0–5) – D0–D5
The color of the PIP can be adjusted to suit viewer
preference by setting the value stored in these bits. A total of
64 steps varies the color from no color to maximum. This
control acts in conjunction with the auto phase control.
PIP Tint Level Register
Sub–address = 09h
Tint (T0–5) – D0–D5
An auto phase control compares the main color burst to
the internally generated pseudo color burst so that the tints
are matched. In addition to this, the tint of the PIP can be
varied
±
10
°
in a total of 64 steps by changing the value of
these bits to suit viewer preference.
PIP Luma Delay Register
Sub–address = 0Ah
Y Delay (YDL0–2) – D0–D2
Since the Chroma passes through a bandpass filter and
the color decoder, it is delayed with respect to the Luma
signal. Therefore, to time match the Luma and Chroma these
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bits are set to a single value determined to be correct in the
application.
PIP Acquire/Playback Register
Sub–address = 0Bh
PIP Acquire Speed Bits (ACQ_SP0–1) – D0–D1
These select the speed of the video acquisition. This is
only active when RE_AQ = 1.
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PIP Save/Clear Bit (RE_AQ) –D2
This bit controls the save and clear function for the instant
replay. The bit value 1 is only effective when PON0–3 = 0000.
(No PIP display.)
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00
Acquire 1 Out of Every 4 Fields
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PIP Playback Speed Bits (PB_SP0–1) – D4–D5
These bits control the relative playback speed, to the
acquired speed.
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This bit controls the start/stop of the instant replay
PB_SP (5:4)
Function
Playback at 1 x ACQ_SP Speed
Playback at 1/2 x ACQ_SP Speed
Playback at 1/4 x ACQ_SP Speed
01
10
11
Playback at 1/8 x ACQ_SP Speed
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00
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PIP Fill/Background/Free Run/Test Register
Sub–address = 0Ch
PIP Fill Bits (PIPFILL0–1) – D0–D1
May be used to fill the PIP with one of three selectable
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Test Register Bits (INTC0 and MACR0) – D6–D7
When the FRUN is set to 1 the circuitry provides a
generated sync and displays a flat field that can be either
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BGND (2:2)
Function
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1
0
Blue
50% White
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