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參數(shù)資料
| 型號： | MC44829D |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | TV AND VCR I2C PLL TUNING CIRCUIT WITH 1.3 GHz PRESCALER AND MIX/OSC DECODER |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO14 |
| 封裝： | PLASTIC, SO-14 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 137K |
| 代理商： | MC44829D |
MC44829
7
MOTOROLA ANALOG IC DEVICE DATA
1.0 nF
÷
8
Pres
Figure 6. Typical Tuner Application
6
7
8
B6
B5
B4
12 pF
3.2/4.0 MHz
Gnd
2
1
14
B III
VHF
UHF
AGC
VTUN
Phase
Comp
2.7 V
Mixer
B. P. Filter
Antenna
Filter
Oscillator
IF
5
5.0 V
11
10
9
13
Osc &
Ref Div
3
4
Fosc
SDA
SCL
CA
Bus
Rec
22 nF
47 k
(Note)
330 p
47 nF
NOTE:
C2 = 330 pF minimum is required for stability.
MC44829
PNP Current
Buffers
Band Decoder
RL
1.0 nF
33 V
Program
Divider
12
M/O
Bits B4, B5, B6: Control the Band Buffers
B4, B5, B6 = 0
B0, B1, B3
= 1
Buffer “Off”
Buffer “On”
Bit T8: Controls the Output of the Operational Amplifier
T8 = 0
Normal Operation
Operational Amplifier Active
Output State of Operational Amplifier Switched “Off”,
Output Pulls High Through the External Pull–Up
Resistor RL
T8
= 1
Bits T9, T12: Control the Phase Comparator
T9
T12
1
1
0
0
1
Function
0
1
0
Normal Operation
High Impedance (Tri–State)
Upper Source “On” Only
Lower Source “On” Only
Bits T10, T11: Control the Reference Divider
T10
T11
0
0
1
1
1
Division Ratio
0
1
0
512
1024
1024
512
Bit T13: Switches the Internal Signals Fref and FBY2 to
Bit T13:
the Band Buffer Outputs (Test)
T13 = 0
T13
= 1
Test Mode
Fref Output at B5 (Pin 7)
FBY2 Output at B6 (Pin 8)
Normal Operation
Bits B5 and B6 have to be “On”, B5 = B6 = 1 in the test mode.
Fref is the reference frequency.
FBY2 is the output frequency of the programmable divider, divided by two.
Bit T14: Controls the Charge Pump Current of the
Bit T14:
Phase Comparator
T14 = 0
T13
= 1
Normal Operation. Pump Current 125
μ
A Typical
Pump Current 40
μ
A Typical
Mixer/Oscillator Band Decoder
The band decoder provides the band switching signal for
the mixer/oscillator circuit. The buffer bits B4 and B6 control
the decoder output. B5 is not decoded. The decoder is
controlled by the buffer bits as per the table below.
B6
0
0
B5
X
X
B4
0
1
Decoder Output DEC
1
1
X
X
0
1
Undefined
3.4 V to VCC1
(VCC1 = 4.5 to 5.5 V)
0 to 0.8 V
1.8 to 2.1 V
BA_Band Information
X
B6
B5
B4
X
X
X
X
ACK
The band buffers are open collector buffers and are active
“l(fā)ow” at Bn = 1. They are designed for 5.0 mA with a typical
“on” voltage of 160 mV. These buffers are designed to
withstand relative high output voltage in the “off” state.
B5 and B6 buffers may also be used to output internal IC
signals (reference frequency and programmable divider
output frequency divided by 2) for test purposes.
The bit B5 and/or B6 have to be one if the buffers are used
for these additional functions.
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
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