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參數(shù)資料
| 型號： | MC44864 |
| 廠商： | Motorola, Inc. |
| 英文描述： | PLL TUNING CIRCUIT WITH 1.3 GHz PRESCALER AND D/A CONVERTERS |
| 中文描述： | 鎖相環(huán)調(diào)諧電路與1.3 GHz的分頻器和D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 203K |
| 代理商： | MC44864 |
MC44864
10
MOTOROLA ANALOG IC DEVICE DATA
Input Data
R f Di id
Ref Divider
Ref. Divider
Div. Ratio
R f F
Ref Freq
Hz(1)
With Int. Prescaler
P = 0
Without Prescaler
P = 1
Frequency
Steps kHz
Max Input
Max. Input
Freq. MHz
Frequency
Steps kHz
Max Imput
Max. Imput
Freq. MHz
R0
0
1
0
1
R1
0
0
1
1
2048
1024
512
256
1953.125
3906.25
7812.5
15625.0
15.625
31.25
62.5
125.0
512
1024
1300(2)
1300(2)
1.953125
3.90625
7.8125
15.625
64
128
165(3)
165(3)
NOTES:
1.With 4.0 MHz Crystal
2.Limit of Prescaler
3.Limit of Programmable Divider
For satellite tuner applications the circuit may be used with an external /4 prescaler and a reference divider ration of 1024 (R0 = 1, R1 = 0). In this way,
frequencies up to 4.0 GHz can be synthesized with 125 kHz resolution (4.0 MHz crystal).
The same result can be achieved with an external /32 prescaler when the internal prescaler is bypassed (P = 1).
The Reference Divider
The reference divider of the MC44864 is programmable
(Bits R0 and R1) for ratios of 2048, 1024, 512 and 256. This
feature makes the circuit versatile.
Bit P: Controls the Prescaler
P
Prescaler Function
0
1
Prescaler Active
Prescaler Bypassed
Prescaler Power Supply “Off”
Bits B1, B3, B5, B7: Controls the Band Buffers
B1, B3, B5, B7 = 0
B0, B1, B, B73
= 1
Buffer “Off”
Buffer “On”
D/A SECTION
Basic Function
The D/A section has four separate chip addresses from
the PLL section. Three D–to–A converters that have a
resolution of 6 bits (5 bits plus sign) are on chip. The analog
output voltages are dc. The converters are buffered to the
analog outputs DA1, DA2 and DA3 by operational amplifiers
with an output voltage range that is equal to the tuning
voltage range (about 0 to 30 V). The operational amplifiers
are arranged such that a positive or negative offset can be
generated from the tuning voltage.
Data Format and Bus Protocols
The D–to–A information consists of the D/A chip address
(CA2) and four data bytes. The first two bits of the data bytes
are used as the function address. Thus the bytes C1, C2 and
C3 contain the address for the individual converter and the 6
bits to be converted. Bit D5 is the sign (log “1” for positive
offset, log “0” for negative offset) and the bits D0 to D4
determine the number of steps to be made as an offset from
the tuning voltage. The bits S0 and S1 in the data byte RA
define the step size (Vstep) and the range of the converters
(see Figures 8 and 9). The range is the same for all
converters.
After the chip address (CA2) is acknowledged, up to four
data bytes may be received by the IC. If more than four bytes
are received, the fifth and following bytes are ignored and the
last acknowledge pulse is sent after the fourth data byte. The
data transfer to the converters (signal DTC) is initiated each
time a complete data byte is received.
The following shows some examples of the permissible
bus protocols of the D–to–A section. The data bytes may be
sent to the IC in random order with up to four in one
sequence. The same converter may be loaded up to four
times as shown in example 6. Below are 6 examples of
permissible bus protocols.
Ex. 1
STA
CA2
C1
STO
Ex. 2
STA
CA2
C1
C2
Ex. 3
STA
CA2
C1
C2
Ex. 4
STA
CA2
C1
C2
Ex. 5
STA
CA2
RA
C1
Ex. 6
STA
CA2
C1
C1
STA = Start Condition
STO = Stop Condition
CA2 = Chip Address Byte for D/A Section
C1, C2, C3 = Data Bytes for D/A Converters
RA = Data Byte for Range
STO
C3
C3
C2
C1
STO
RA
C3
C1
STO
STO
STO
Figure 7. Definition of Bytes
CA2_D/A Chip Address
ééééééééééééééééééééééé
ééééééééééééééééééééééé
C1_Converter 1
ééééééééééééééééééééééé
ééééééééééééééééééééééé
C2_Converter 2
ééééééééééééééééééééééé
ééééééééééééééééééééééé
C3_Converter 3
ééééééééééééééééééééééé
ééééééééééééééééééééééé
RA_Range Selection
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