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參數(shù)資料
| 型號： | MC44BS373CAFCR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 16/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MODULATOR AUD/VID U/V 20-QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | NTSC/PAL 調(diào)制器 |
| 應(yīng)用： | 音頻/視頻，VCR，機(jī)頂盒 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN 裸露焊盤（5x5） |
| 包裝： | 帶卷 (TR) |
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MC44BS373CA Data Sheet
MC44BS373CA Modes of Operation
15.5 Transient Output Inhibit
To minimize the risk of interference to other channels while the UHF PLL is acquiring a lock on the desired
frequency, the sound and video modulators are turned off during a timeout period for the following cases:
Power-on from zero (that is, all VCC switched from 0 to 5 V)
UHF oscillator power-on from off state (that is, OSC bit switched from 1 to 0)
There is a timeout of 263 ms until the output is enabled. This lets the UHF PLL settle to its programmed
frequency. During the 263-ms timeout, the sound PLL current source is set to 10
A typical to speed up the
locking time. After the timeout, the current source is switched to 1
A. Use care when selecting loop filter
components to ensure the loop transient does not exceed this delay.
For test purposes, it is possible to disable the 263-ms delay using test mode1, state1.h. (This is called
speed-up mode.) Table 17 provides settings pertaining to test mode 1.
15.6 UHF Oscillator—VHF range
The UHF oscillator is fully integrated and does not require any external components.
For low-frequency testing or VHF range operation (test mode 1, states 1.b to 1.e) the UHF oscillator can be
internally divided by 2, 4, 8, or 16.
15.7 UHF PLL Section
The reference divider is a fixed divide-by-128, resulting in a reference frequency of 31.25 kHz with a
4.0-MHz crystal.
The prescaler is a fixed divide-by-8 and is permanently engaged.
The programmable divider division ratio is controlled by the state of control bits N0 to N11.
The divider ratio N for a desired frequency F (in MHz) is given by:
with:
NOTE
Programming a division ratio of N = 0 is not allowed.
15.8 Logic Output Port (LOP)
The LOP pin controls any logic function. The primary applications for LOP are to control an external
attenuator or an external switch between the antenna input and TV output. A typical attenuator application
with PIN diode is shown in Figure 6. The LOP pin switches the PIN attenuator depending on the signal
strength of the antenna input. This reduces the risk of intermodulation in certain areas. The LOP can also be
used as an off position bypass switch or for other logic functions in the application.
N
F
8
---
128
4
----------
×
=
N
2048
N11
×
1024
N10
×…… 4 N2
×
4
N1
×
N0
++
+
=
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC44BS373CAR2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PLL-Tuned UHF and VHF Audio/Video High-Integration Modulator |
| MC44BS373CR2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PLL-Tuned UHF and VHF Audio/Video High-Integration Modulator |
| MC44BS374 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MC44BS374 |
| MC44BS374CA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SO16NB Package |
| MC44BS374CAD | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:CMOS Audio/Video RF Modulators |
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