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參數(shù)資料
| 型號： | MC54-74HC374A |
| 廠商： | Motorola, Inc. |
| 英文描述： | Octal 3-State Non-Inverting D Flip-Flop |
| 中文描述： | 八路三態(tài)非反相D觸發(fā)器 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 253K |
| 代理商： | MC54-74HC374A |
MC54/74HC374A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA
0.10
|Iout|
20
μ
A
Voltage
0.10
4.5
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Vout = VCC or GND
0.26
±
0.1
0.10
Vin = VIH or VIL
|Iout|
|Iout|
|Iout|
6.0
±
0.5
0.33
0.40
V
Iin
IOZ
Maximum Three–State
Leakage Current
Maximum Input Leakage Current
Output in High–Impedance State
Vin = VIL or VIH
Vin = VCC or GND
6.0
±
1.0
±
1.0
μ
A
6.0
±
5.0
±
10
μ
A
Current (per Package)
Iout = 0
μ
A
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6.0 ns)
Speed CMOS Data Book (DL129/D).
Symbol
b l
Parameter
V
25 C
35
28
U i
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
4.5
6.0
30
26
150
125 C
30
26
33
Maximum Clock Frequency (50% Duty Cycle)
2.0
6.0
21
6
45
38
5
4
24
MHz
Maximum Propagation Delay, Input Clock to Q
4.5
6.0
2.0
6.0
125
155
26
32
45
38
190
ns
tPLZ
Maximum Propagation Delay, Output Enable to Q
2.0
15
190
38
33
225
ns
tPLZ
4.5
6.0
Maximum Propagation Delay, Output Enable to Q
2.0
150
22
190
38
225
tTLH
Maximum Output Transition Time, Any Output
2.0
75
10
95
19
110
10
CPD
Power Dissipation Capacitance (Per Enabled Output)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
bl d O
Typical @ 25
°
C, VCC = 5.0 V
34
pF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC74HC374A | Octal 3-State Non-Inverting D Flip-Flop |
| MC74HC374ADT | Octal 3-State Non-Inverting D Flip-Flop |
| MC74HC374ADW | Octal 3-State Non-Inverting D Flip-Flop |
| MC74HC374ADWR2 | Octal 3-State Non-Inverting D Flip-Flop |
| MC74HC374ADTR2 | Octal 3-State Non-Inverting D Flip-Flop |
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