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參數資料
| 型號： | MC54HCT00AJ |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad 2-Input NAND Gate with LSTTL-Compatible Inputs |
| 中文描述： | HCT SERIES, QUAD 2-INPUT NAND GATE, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁數： | 2/5頁 |
| 文件大?。?/td> | 172K |
| 代理商： | MC54HCT00AJ |
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
2
500
Storage Temperature
SOIC Package
– 65 to + 150
C
260
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
SOIC or Plastic Package
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Min
2.0
Max
6.0
Unit
V
DC CHARACTERISTICS
FOR THE MC54/74HCT00A
(Voltages Referenced to GND)
Guaranteed Limits
Minimum High–Level
Input Voltage
|Iout|
20
A
Vout = 0.1 or VCC – 0.1 V
|Iout|
20
μ
A
Vin = VIH or VIL
|Iout| = 4.0 mA
Vin = VCC or GND
4.5
5.5
2.00
2.00
2.00
2.00
2.00
2.00
VIL
Maximum Low–Level
4.5
0.80
0.80
0.80
V
Output Voltage
5.5
5.40
5.40
5.40
V
4.5
0.26
0.33
0.40
Iin
Maximum Input Leakage
5.5
±
0.10
±
1.00
±
1.00
ply Current (per Package)
0
A
Vin = 2.4 V, Any One Input
μ
A
Additional Quiescent
– 55 C
25 to 125 C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
3
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