- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄1948 > MC56F8014MFAE (Freescale Semiconductor)IC DIGITAL SIGNAL CTLR 32-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | MC56F8014MFAE |
| 廠(chǎng)商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 105/124頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DIGITAL SIGNAL CTLR 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,250 |
| 系列： | 56F8xxx |
| 核心處理器： | 56800E |
| 芯體尺寸： | 16-位 |
| 速度： | 32MHz |
| 連通性： | I²C，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲(chǔ)器容量： | 16KB（8K x 16） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 2K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 32-LQFP |
| 包裝： | 托盤(pán) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)當(dāng)前第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)
Clocks
56F8014 Technical Data, Rev. 11
Freescale Semiconductor
81
6.7 Clocks
The memory, peripheral and core clocks all operate at the same frequency (32MHz max) with the
exception of the TMR and PWM peripheral clocks, which have the option (using TCR and PCR) to operate
three times faster. The SIM is responsible for stalling individual clocks as a response to various hold-off
requests, low power modes, and other configuration parameters. The SIM has access to the following
signals from the OCCS module:
While the SIM generates the ADC peripheral clock in the same way it generates all other peripheral clocks,
the ADC standby and conversion clocks are generated by a direct interface between the ADC and the
OCCS module.
Figure 6-16 illustrates clock relationships to one another and to the various resets as the device comes out
of reset. RST is assumed to be the logical AND of all active-low system resets (for example, POR, external
reset, COP and Software reset). In the 56F8014 architecture, this signal will be stretched by the SIM for a
period of time (up to 96 MSTR_OSC clock cycles, depending upon the status of the POR) to create the
clock generation reset signal (CLKGEN_RST). The SIM should deassert CLKGEN_RST synchronously
with the negative edge of OSC_CLK in order to avoid skew problems. CLKGEN_RST is delayed 32
SYS_CLK cycles to create the peripheral reset signal (PERIP_RST). PERIP_RST is then delayed by 32
SYS_CLK cycles to create CORE_RST. Both PERIP_RST and CORE_RST should be released on the
negative edge of SYS_CLK_D as shown. This phased releasing of system resets is necessary to give some
peripherals (for example, the Flash interface unit) set-up time prior to the 56800E core becoming active.
MSTR_OSC
This comes from the input clock source mux of the OCCS. It is the output of the relaxation
oscillator or the external clock source, depending on PRECS. It is not guaranteed to be at
50% duty cycle (+ or - 10% can probably be assumed for design purposes). This clock runs
continuously, even during reset and is used for reset generation.
HS_PERF
The PLL multiplies the MSTR_OSC by 24, to a maximum of 192MHz. The ZSRC field in
OCCS selects the active source to be the PLL. This is divided by 2 and postscaled to
produce this maximum 96MHz clock. It is used without further division to produce the
high-speed (3x system bus rate) variants of the Quad Timer and PWM peripheral clocks.
This clock is disabled when ZSRC is selecting MSTR_OSC.
SYS_CLK_x2
The PLL can multiply the MSTR_OSC by 24, to a maximum of 192MHz. When the PLL is
selected by the OCCS ZSRC field, the PLL is divided by three and postscaled to produce
this maximum 64MHz clock. When MSTR_OSC is selected by the OCCS ZSRC field,
MSTR_OSC feeds SYS_CLK_x2 directly. The SIM takes this clock and divides it by two to
generate all the normal (1x system bus rate) peripheral and system clocks.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC56F8023VLC | IC DSP 16BIT DUAL HARV 32-LQFP |
| MC56F8025VLD | IC DSP 16BIT DUAL HARV 44-LQFP |
| MC56F8036VLF | IC DGTL SGNL CTLR 16BIT 48-LQFP |
| MC56F8037VLH | IC DSP 16BIT DUAL 64-LQFP |
| MC56F8135VFGE | IC DIGITAL SIGNAL CTLR 128-LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC56F8014VFAE | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT DSPHC BAHAMAS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MC56F8023 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8023VLC | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT DSPHC RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MC56F8025 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8025E | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Digital Signal Controller Product Brief |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。