參數資料
型號： MC56F8023VLC
廠商： Freescale Semiconductor
文件頁數： 6/157頁
文件大?。?/td> 0K
描述： IC DSP 16BIT DUAL HARV 32-LQFP
標準包裝： 1,250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，LIN，SCI，SPI
外圍設備： POR，PWM，WDT
輸入/輸出數： 26
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數據轉換器： A/D 6x12b; D/A 2x12b
振蕩器型： 內部
工作溫度： -40°C ~ 105°C
封裝/外殼： 32-LQFP
包裝： 托盤
Power-Saving Modes
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor
103
6.5 Power-Saving Modes
The 56F8033/56F8023 operates in one of five Power-Saving modes, as shown in Table 6-2
The power-saving modes provide additional power management options by disabling the clock,
reconfiguring the voltage regulator clock generation to manage power utilization, as shown in Table 6-2.
Run, Wait, and Stop modes provide methods of enabling/disabling the peripheral and/or core clocking as
a group. Stop disable controls for an individual peripheral are provided in the SDn registers to override the
Table 6-2 Clock Operation in Power-Saving Modes
Mode
Core Clocks
Peripheral Clocks
Description
Run
Core and memory
clocks enabled
Peripheral clocks
enabled
Device is fully functional
Wait
Core and memory
clocks disabled
Peripheral clocks
enabled
Core executes WAIT instruction to enter this
mode.
Typically used for power-conscious applications.
Possible recoveries from Wait mode to Run
mode are:
1. Any interrupt
2. Executing a Debug mode entry command
during the 56800E core JTAG interface
3. Any reset (POR, external, software, COP)
Stop
Master clock generation in the OCCS
remains operational, but the SIM disables
the generation of system and peripheral
clocks.
Core executes STOP instruction to enter this
mode.
Possible recoveries from Stop mode to Run
mode are:
1. Interrupt from any peripheral configured in the
CTRL register to operate in Stop mode (TA0-3,
QSCI0, PIT0-1, CAN, CMPA-B)
2. Low-voltage interrupt
3. Executing a Debug mode entry command
using the 56800E core JTAG interface
4. Any reset (POR, external, software, COP)
Standby
The OCCS generates the master clock at a
reduced frequency (400kHz). The PLL is
disabled and the high-speed peripheral
option is not available. System and
peripheral clocks operate at 200kHz.
The user configures the OCCS and SIM to select
the relaxation oscillator clock source (PRECS),
shut down the PLL (PLLPD), put the relaxation
oscillator in Standby mode (ROSB), and put the
large regulator in Standby (LRSTDBY). The
device is fully operational, but operating at a
minimum frequency and power configuration.
Recovery requires reversing the sequence used
to enter this mode (allowing for PLL lock time).
Power-Down
Master clock generation in the OCCS is
completely shut down. All system and
peripheral clocks are disabled.
The user configures the OCCS and SIM to enter
Standby mode as shown in the previous
description, followed by powering down the
oscillator (ROPD). The only possible recoveries
from this mode are:
1. External Reset
2. Power-On Reset
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