參數(shù)資料
型號: MC56F8156VFVE
廠商: Freescale Semiconductor
文件頁數(shù): 89/178頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 40MHZ 144-LQFP
標準包裝: 60
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 40MHz
連通性: EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 62
程序存儲器容量: 256KB(128K x 16)
程序存儲器類型: 閃存
RAM 容量: 8K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 144-LQFP
包裝: 托盤
56F8356 Technical Data, Rev. 13
18
Freescale Semiconductor
Preliminary
2.2 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other
states show the reset condition of the alternate function, which you get if the alternate pin function is
selected without changing the configuration of the alternate peripheral. For example, the A8/GPIOA0 pin
shows that it is tri-stated during reset. If the GPIOA_PER is changed to select the GPIO function of the
pin, it will become an input if no other registers are changed.
Table 2-2 Signal and Package Information for the 144-Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
VDD_IO
1
Supply
I/O Power — This pin supplies 3.3V power to the chip I/O interface
and also the Processor core throught the on-chip voltage
regulator, if it is enabled.
VDD_IO
16
VDD_IO
31
VDD_IO
38
VDD_IO
66
VDD_IO
84
VDD_IO
119
VDDA_ADC
102
Supply
ADC Power — This pin supplies 3.3V power to the ADC modules.
It must be connected to a clean analog power supply.
VDDA_OSC_PLL
80
Supply
Oscillator and PLL Power — This pin supplies 3.3V power to the
OSC and to the internal regulator that in turn supplies the Phase
Locked Loop. It must be connected to a clean analog power
supply.
VSS
27
Supply
VSS — These pins provide ground for chip logic and I/O drivers.
VSS
37
VSS
63
VSS
69
VSS
144
VSSA_ADC
103
Supply
ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
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