參數(shù)資料
型號： MC56F8345VFG60
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： 56F8345 16-bit Hybrid Controller
中文描述： 0-BIT, 240 MHz, OTHER DSP, PQFP128
封裝： 14 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-128
文件頁數(shù)： 101/148頁
文件大?。?/td> 1420K
代理商： MC56F8345VFG60
Register Descriptions
56F8345 Technical Data
Preliminary
101
6.5.6.6
This bit controls the pull-up resistors on the IRQA and IRQB pins.
IRQ—Bit 10
6.5.6.7
This bit controls the pull-up resistors on the EXTBOOT pin.
XBOOT—Bit 9
Note:
In this package, this input pin is double-bonded with the adjacent V
SS
pin and this bit should
be changed to a 1 in order to reduce power consumption.
6.5.6.8
This bit controls the pull-up resistors on the FAULTB0, FAULTB1, FAULTB2, and FAULTB3
pins.
PWMB—Bit 8
6.5.6.9
This bit controls the pull-up resistors on the FAULTA0, FAULTA1, and FAULTA2 pins.
PWMA0—Bit 7
6.5.6.10 Reserved—Bit 6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.11 CTRL—Bit 5
This bit controls the pull-up resistors on the WR and RD pins.
6.5.6.12 Reserved—Bit 4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.13 JTAG—Bit 3
This bit controls the pull-up resistors on the TRST, TMS and TDI pins.
6.5.6.14 Reserved—Bit 2–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7
The CLKO select register can be used to multiplex out any one of the clocks generated inside the
clock generation and SIM modules. The default value is SYS_CLK. This path has been optimized
in order to minimize any delay and clock duty cycle distortion. All other clocks primarily muxed
out are for test purposes only, and are subject to significant phase shift at high frequencies.
CLKO Select Register (SIM_CLKOSR)
The upper four bits of the GPIO B register can function as GPIO A23 through A20, or as additional
clock output signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIO
B[7:4] are programmed to operate as peripheral outputs, then the choice between A23 through A20
and additional clock outputs is done here in the CLKOSR. The default state is for the peripheral
function of GPIO B[7:4] to be programmed as A23 through A20. This can be changed by altering
A23 through A20, as shown in
Figure 6-9
.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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相關代理商/技術參數(shù)
參數(shù)描述
MC56F8345VFGE 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MC56F8346 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
MC56F8346EVM 制造商:Freescale Semiconductor 功能描述:Tools Development kit Kit Contents:Inst
MC56F8346MFV60 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 60MHz 60MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MC56F8346MFVE 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
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