參數(shù)資料
型號: MC56F8355MFGE
廠商: Freescale Semiconductor
文件頁數(shù): 145/172頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 60MHZ 128-LQFP
標準包裝: 72
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 49
程序存儲器容量: 264KB(132K x 16)
程序存儲器類型: 閃存
RAM 容量: 10K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 128-LQFP
包裝: 托盤
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8355 Technical Data, Rev. 17
74
Freescale Semiconductor
Preliminary
5.3.3
Fast Interrupt Handling
Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes fast
interrupts before the core does.
A fast interrupt is defined (to the ITCN) by:
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers
2. Setting the FIMn register to the appropriate vector number
3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a
match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN takes the vector
address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an
offset from the VBA.
The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts
its fast interrupt handling.
01
Priority 0
Priorities 1, 2, 3
10
Priority 1
Priorities 2, 3
11
Priorities 2 or 3
Priority 3
1. See IPIC field definition in Part 5.6.30.2
Table 5-2 Interrupt Priority Encoding
IPIC_LEVEL[1:0]1
Current Interrupt
Priority Level
Required Nested
Exception Priority
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