參數(shù)資料
型號(hào): MC56F8357VPY60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-bit Digital Signal Processor
中文描述: 16-BIT, 240 MHz, OTHER DSP, PQFP160
封裝: 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-160
文件頁數(shù): 7/160頁
文件大?。?/td> 1394K
代理商: MC56F8357VPY60
Architecture Block Diagram
56F8357 Technical Data
Preliminary
7
1.4 Architecture Block Diagram
The 56F8357 architecture is shown in
Figure 1-1
and
Figure 1-2
.
Figure 1-1
illustrates how the
56800E system buses communicate with internal memories, the external memory interface and the
IPBus Bridge.
Table 1-1
lists the internal buses in the 56800E architecture and provides a brief
description of their function.
Figure 1-2
shows the peripherals and control blocks connected to the
IPBus Bridge. The figures do not show the on-board regulator and power and ground signals. They
also do not show the multiplexing between peripherals or the dedicated GPIOs. Please see
Section 2, Signal/Connection Descriptions,
to see which signals are multiplexed with those of
other peripherals.
Also shown in
Figure 1-2
are connections between the PWM, Timer C and ADC blocks. These
connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions.
The Timer C channel indicated can generate periodic start (SYNC) signals to the ADC to start its
conversions. In another operating mode, the PWM load interrupt (SYNC output) signal is routed
internally to the Timer C input channel as indicated. The timer can then be used to introduce a
controllable delay before generating its output signal. The timer output then triggers the ADC. To
fully understand this interaction, please see the
56F8300 Peripheral User Manual
for clarification
on the operation of all three of these peripherals.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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