
MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL
2-11
Table 2-2. Instruction Set Summary (Sheet 1 of 4)
Opcode
Operation
Syntax
ABCD
Source10 + Destination10 + X
→
Destination
ABCD Dy,Dx
ABCD –(Ay), –(Ax)
ADD
Source + Destination
→
Destination
ADD <ea>,Dn
ADD Dn,<ea>
ADDA
Source + Destination
→
Destination
Immediate Data + Destination
→
Destination
Immediate Data + Destination
→
Destination
Source + Destination + X
→
Destination
ADDA <ea>,An
ADDI
ADDI # <data>,<ea>
ADDQ
ADDQ # <data>,<ea>
ADDX
ADDX Dy, Dx
ADDX –(Ay), –(Ax)
AND
Source
Λ
Destination
→
Destination
AND <ea>,Dn
AND Dn,<ea>
ANDI
Immediate Data
Λ
Destination
→
Destination
ANDI to CCR Source
Λ
CCR
→
CCR
ANDI # <data>, <ea>
ANDI # <data>, CCR
ANDI to SR
If supervisor state
then Source
Λ
SR
→
SR
else TRAP
ANDI # <data>, SR
ASL, ASR
Destination Shifted by <count>
→
Destination
ASd Dx,Dy
ASd # <data>,Dy
ASd <ea>
Bcc
If (condition true) then PC + d
→
PC
~ (<number> of Destination)
→
Z;
~ (<number> of Destination)
→
<bit number> of Destination
~ (<bit number> of Destination)
→
Z;
0
→
<bit number> of Destination
Bcc <label>
BCHG
BCHG Dn,<ea>
BCHG # <data>,<ea>
BCLR
BCLR Dn,<ea>
BCLR # <data>,<ea>
BKPT
Run breakpoint acknowledge cycle;
TRAP as illegal instruction
BKPT # <data>
BRA
PC + d
→
PC
~ (<bit number> of Destination)
→
Z;
1
→
<bit number> of Destination
SP – 4
→
SP; PC
→
(SP); PC + d
→
PC
– (<bit number> of Destination)
→
Z;
BRA <label>
BSET
BSET Dn,<ea>
BSET # <data>,<ea>
BSR
BSR <label>
BTST
BTST Dn,<ea>
BTST # <data>,<ea>
CHK
If Dn < 0 or Dn > Source then TRAP
CHK <ea>,Dn
CLR
0
→
Destination
Destination—Source
→
cc
CLR <ea>
CMP
CMP <ea>,Dn
CMPA
Destination—Source
CMPA <ea>,An
CMPI
Destination —Immediate Data
CMPI # <data>,<ea>
CMPM
Destination—Source
→
cc
If condition false then (Dn – 1
→
Dn;
If Dn
≠
–1 then PC + d
→
PC)
CMPM (Ay)+, (Ax)+
DBcc
DBcc Dn,<label>