
5-10
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
MOTOROLA
The interrupt acknowledge cycle places the level of the interrupt being acknowledged on
address bits A3–A1 and drives all other address lines high. The interrupt acknowledge
cycle reads a vector number when the interrupting device places a vector number on the
data bus and asserts
DTACK
to acknowledge the cycle.
The timing diagram for an interrupt acknowledge cycle is shown in Figure 5-11.
Alternately, the interrupt acknowledge cycle can be autovectored. The interrupt
acknowledge cycle is the same, except the interrupting device asserts
VPA
instead of
DTACK
. For an autovectored interrupt, the vector number used is $18 plus the interrupt
level. This is generated internally by the microprocessor when
VPA
(or
AVEC
) is asserted
on an interrupt acknowledge cycle.
DTACK
and
VPA
(
AVEC
) should never be
simultaneously asserted.
CLK
FC2–FC0
A23–A4
AS
UDS
*
LDS
R/W
DTACK
D15–D8
D7–D0
IPL2–IPL0
STACK
PCL
(SSP)
IACK CYCLE
(VECTOR NUMBER
ACQUISITION)
STACK AND
VECTOR
FETCH
A3–A1
Although a vector number is one byte, both data strobes are asserted due to the mcrocode used for exception processing. The processor does not
recognize anything on data lines D8 through D15 at this time.
LAST BUS CYCLE OF INSTRUCTION
(READ OR WRITE)
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 w
w
w
w S5 S6
*
IPL2–IPL0 TRANSITION
IPL2–IPL0 SAMPLED
IPL2–IPL0 VALID INTERNALLY
Figure 5-11. Interrupt Acknowledge Cycle Timing Diagram