參數(shù)資料
型號(hào)： MC68040RC25A
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 212/442頁(yè)
文件大?。?/td> 0K
描述： IC MICROPROCESSOR 32BIT 179-PGA
標(biāo)準(zhǔn)包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 25MHz
電壓： 5V
安裝類型： 通孔
封裝/外殼： 179-BPGA
供應(yīng)商設(shè)備封裝： 179-PGA（47.24x47.24）
包裝： 托盤
1- 8
M68040 USER’S MANUAL
MOTOROLA
The user programming model includes eight data registers, seven address registers, and
a stack pointer register. The address registers and stack pointer can be used as base
address registers or software stack pointers, and any of the 16 registers can be used as
index registers. Two control registers are available in the user mode—the program
counter (PC), which usually contains the address of the instruction that the MC68040 is
executing, and the lower byte of the SR, which is accessible as the condition code register
(CCR). The CCR contains the condition codes that reflect the results of a previous
operation and can be used for conditional instruction execution in a program.
The supervisor programming model includes the upper byte of the SR, which contains
operation control information. The vector base register (VBR) contains the base address
of the exception vector table, which is used in exception processing. The source function
code (SFC) and destination function code (DFC) registers contain 3-bit function codes.
These function codes can be considered extensions to the 32-bit logical address. The
processor automatically generates function codes to select address spaces for data and
program accesses in the user and supervisor modes. Some instructions use the alternate
function code registers to specify the function codes for various operations.
The cache control register (CACR) controls enabling of the on-chip instruction and data
caches of the MC68040. The supervisor root pointer (SRP) and user root pointer (URP)
registers point to the root of the address translation table tree to be used for supervisor
and user mode accesses.
The translation control register (TCR) enables logical-to-physical address translation and
selects either 4- or 8-Kbyte page sizes. There are four transparent translation registers,
two for instruction accesses and two for data accesses. These registers allow portions of
the logical address space to be transparently mapped and accessed without the use of
resident descriptors in an ATC. The MMU status register (MMUSR) contains status
information derived from the execution of a PTEST instruction. The PTEST instruction
searches the translation tables for the logical address, specified by this instruction’s
effective address field and the DFC, and returns status information corresponding to the
translation.
The user programming model can also access the entire floating-point programming
model. The eight 80-bit floating-point data registers are analogous to the integer data
registers. A 32-bit floating-point control register (FPCR) contains an exception enable byte
that enables and disables traps for each class of floating-point exceptions and a mode
byte that sets the user-selectable rounding and precision modes. A floating-point status
register (FPSR) contains a condition code byte, quotient byte, exception status byte, and
accrued exception byte. A floating-point exception handler can use the address in the 32-
bit floating-point instruction address register (FPIAR) to locate the floating-point instruction
that has caused an exception. Instructions that do not modify the FPIAR can be used to
read the FPIAR in the exception handler without changing the previous value.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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